Logic rectification and synthesis for engineering change

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 1995, Pages 301-309

  Lin, Chih chang ^a   Chen, Kuang Chien ^a   Cheng, David Ihsin ^a   Marek Sadowska, Malgorzata ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; ELECTRIC NETWORK SYNTHESIS; ERROR CORRECTION; LOGIC CIRCUITS; LOGIC GATES; MODIFICATION; OPTIMIZATION; VLSI CIRCUITS;

ENGINEERING CHANGE PROBLEM; LOGIC RECTIFICATION; LOGIC SYNTHESIS; LOGIC TRANSFORMATION; MULTIPLE ERROR DIAGNOSIS;

LOGIC DESIGN;

EID: 0029545197     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)