LOT: Logic optimization with testability - new transformations using recursive learning

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1995, Pages 318-325

  Chatterjee, Mitrajit ^a   Pradhan, Dhiraj K ^a   Kunz, Wolfgang ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; LOGIC DESIGN; LOGIC GATES; OPTIMIZATION; RECURSIVE FUNCTIONS;

GATE BASED TRANSFORMATIONS; LOGIC OPTIMIZATION WITH TESTABILITY (LOT); RANDOM PATTERN TESTABILITY; RECURSIVE LEARNING;

LOGIC CIRCUITS;

EID: 0029544859     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)