Novel contamination restrained silicidation processing using load-lock LPCVD-films and lightly doped deep drain (LD3) structure for deep submicron dual gate CMOS

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1995, Pages 457-460

  Kotaki, H ^a   Nakano, M ^a   Hayashida, S ^a   Matsuoka, T ^a   Kakimoto, S ^a   Nakano, A ^a   Uda, K ^a   Sato, Y ^a  

^a SHARP CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; DIFFUSION; ELECTRIC RESISTANCE; GATES (TRANSISTOR); HIGH TEMPERATURE OPERATIONS; ION IMPLANTATION; LEAKAGE CURRENTS; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING; THERMODYNAMIC STABILITY; TITANIUM COMPOUNDS;

LIGHTLY DOPED DEEP DRAIN STRUCTURE; LOAD LOCKED POLYSILICON; SILICIDATION; TITANIUM DISILICIDE;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0029544645     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)