Scaling scheme for interconnect in deep-submicron processes

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1995, Pages 245-248

  Rahmat, K ^a   Nakagawa, O S ^a   Oh, S Y ^a   Moll, J ^a   Lynch, W T ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; CAPACITANCE; COMPUTER SIMULATION; CROSSTALK; ELECTRIC DELAY LINES; ELECTROMIGRATION; GEOMETRY; INTEGRATED CIRCUIT MANUFACTURE; OPTIMIZATION;

CIRCUIT AND SYSTEM DESIGN TECHNIQUES; CROSSTALK NOISE; DEEP SUBMICRON PROCESS; INTERCONNECT SCALING SCHEME; SOFTWARE PACKAGE SPICE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029544642     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)