Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 1995, Pages 123-125

  Ker, Ming Dou ^a   Wang, Kuo Feng ^a   Joe, Mei Chu ^a   Chu, Yuan Hua ^a   Wu, Tain Shun ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC DISCHARGES; ELECTRIC EQUIPMENT PROTECTION; ELECTROSTATICS; INTEGRATED CIRCUIT LAYOUT; MOS DEVICES; RELIABILITY; SCHEMATIC DIAGRAMS; THYRISTORS;

DEEP SUBMICRON TECHNOLOGIES; ELECTROSTATIC DISCHARGE; ESD PROTECTION; HIGH-DENSITY APPLICATIONS; HUMAN-BODY-MODE; OUTPUT BUFFER;

BUFFER CIRCUITS;

EID: 0029543507     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)