Parallel processor for neural networks

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1995, Pages 81-82

  Lee, Peter ^a   Sartori, Alvise ^a   Tecchiolli, Giampietro ^a   Zorat, Alessandro ^a  

^a UNIVERSITY OF KENT   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; INTEGRATED CIRCUIT MANUFACTURE; LEARNING ALGORITHMS; MULTIPLYING CIRCUITS; NEURAL NETWORKS; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; RANDOM ACCESS STORAGE; VLSI CIRCUITS;

DIGITAL DATA STREAM; INTEGER ARITHMETIC; MULTIPLIERS-ACCUMULATORS; REACTIVE TABU SEARCH; TRAINING ALGORITHM;

PARALLEL PROCESSING SYSTEMS;

EID: 0029542958     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)