-
2
-
-
0025384843
-
A high speed direct frequency synthesizer
-
Feb.
-
P. H. Saul and D. G. Taylor, “A high speed direct frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 25, no. 1, pp. 215–219, Feb. 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, Issue.1
, pp. 215-219
-
-
Saul, P.H.1
Taylor, D.G.2
-
3
-
-
0026938434
-
A monolithic digital chirp synthesizer chip with I and Q channels
-
Oct.
-
V. Andrews, C. T. M. Chang, J. D. Cayo, S. Sabin, W. A, White, and M. P. Harris, “A monolithic digital chirp synthesizer chip with I and Q channels,” IEEE J. Solid-State Circuits, vol. 27, pp. 1321–1326, Oct. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, pp. 1321-1326
-
-
Andrews, V.1
Chang, C.T.M.2
Cayo, J.D.3
Sabin, S.4
White, W.A.5
Harris, M.P.6
-
4
-
-
0026748134
-
Low latency, high-speed numerically controlled oscillator using progression-of-states technique
-
Jan.
-
M. Thompson, “Low latency, high-speed numerically controlled oscillator using progression-of-states technique,” IEEE J. Solid-State Circuits, vol. 27, pp. 113–117, Jan. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, pp. 113-117
-
-
Thompson, M.1
-
5
-
-
84895384046
-
-
U.S. Patent no. 4, 454, 486, Hewlett Packard, June 12
-
R. Hassun and A. W. Kovalick, “Waveform synthesis using multiplexed parallel synthesizers,” U.S. Patent no. 4, 454, 486, Hewlett Packard, June 12, 1984.
-
(1984)
Waveform synthesis using multiplexed parallel synthesizers
-
-
Hassun, R.1
Kovalick, A.W.2
-
6
-
-
0029267943
-
A 200-MHz quadrature frequency synthesizer/mixer in 0.8 µm CMOS
-
Mar.
-
L. K. Tan and H. Samueli, “A 200-MHz quadrature frequency synthesizer/mixer in 0.8 µm CMOS,” IEEE J. Solid-State Circuits, vol. 30, pp. 193–200, Mar. 1995.
-
(1995)
IEEE J. Solid-State Circuits
, vol.30
, pp. 193-200
-
-
Tan, L.K.1
Samueli, H.2
-
7
-
-
0023586546
-
An analysis of the output spectrum of direct digital frequency synthesizers in the presence of phase-accumulator truncation
-
Ft. Monmouth, NJ May
-
H. T. Nicholas (III) and H. Samueli, “An analysis of the output spectrum of direct digital frequency synthesizers in the presence of phase-accumulator truncation,” in Proc. 41st Annual Frequency Control Symp. USERACOM, Ft. Monmouth, NJ, May 1987, pp. 495–502.
-
(1987)
Proc. 41st Annual Frequency Control Symp. USERACOM
, pp. 495-502
-
-
Nicholas, H.T.1
Samueli, H.2
-
8
-
-
0024611252
-
High-speed CMOS circuit technique
-
Feb.
-
J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 62–70, Feb. 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, Issue.1
, pp. 62-70
-
-
Yuan, J.1
Svensson, C.2
-
9
-
-
0002512395
-
Fast CMOS ECL receivers with 100-mV worst case sensitivity
-
Feb.
-
B. A. Chappell, T. I. Chappell, S. E. Schuster, H. M. Segmuller, J. W. Allan, R. L. Franch, and P. J. Restle, “Fast CMOS ECL receivers with 100-mV worst case sensitivity,” IEEE J. Solid-State Circuits, vol. 23, no. 1, pp. 59–67, Feb. 1988.
-
(1988)
IEEE J. Solid-State Circuits
, vol.23
, Issue.1
, pp. 59-67
-
-
Chappell, B.A.1
Chappell, T.I.2
Schuster, S.E.3
Segmuller, H.M.4
Allan, J.W.5
Franch, R.L.6
Restle, P.J.7
-
10
-
-
0024090796
-
A 2-µm CMOS digital adaptive equalizer chip for QAM digital radio modems
-
Oct.
-
S. R. Meier, E. De Man, T. G. Noll, U. Loibl, and H. Klar, “A 2-µm CMOS digital adaptive equalizer chip for QAM digital radio modems,” IEEE J. Solid-State Circuits, vol. 23, no. 5, pp. 1212–1217, Oct. 1988.
-
(1988)
IEEE J. Solid-State Circuits
, vol.23
, Issue.5
, pp. 1212-1217
-
-
Meier, S.R.1
De Man, E.2
Noll, T.G.3
Loibl, U.4
Klar, H.5
|