Laterally etched undercut (LEU) technique to reduce base-collector capacitances in heterojunction bipolar transistors

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

Volumn , Issue , 1995, Pages 167-170

  Liu, William ^a   Hill, Darrell ^a   Chau, Hin Fai ^a   Sweder, Jim ^a   Nagle, Tom ^a   Delaney, J ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC CONTACTS; ELECTRIC CURRENT COLLECTORS; ETCHING; PERFORMANCE; PERMITTIVITY; SEMICONDUCTING ALUMINUM COMPOUNDS; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR JUNCTIONS;

CANTILEVER STRUCTURE; EXTRINSIC BASE COLLECTOR JUNCTION AREAS; LATERALLY ETCHED UNDERCUT PROCESS; PARASITIC JUNCTION CAPACITANCE;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 0029532703     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (26)