Architectures for Hierarchical and Other Block Matching Algorithms

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 5, Issue 6, 1995, Pages 477-489

  Gupta, Gagan ^a   Chakrabarti, Chaitali ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; COMPUTATIONAL COMPLEXITY; DATA STORAGE EQUIPMENT; HIERARCHICAL SYSTEMS; PATTERN RECOGNITION; REAL TIME SYSTEMS; SCHEDULING; SYSTOLIC ARRAYS; VLSI CIRCUITS;

BLOCK MATCHING ALGORITHMS; HIERARCHICAL BLOCK MATCHING; MEMORY ORGANIZATION; MOTION ESTIMATION; ON CHIP MEMORY; SPECIAL PURPOSE ARCHITECTURE;

COMPUTER ARCHITECTURE;

EID: 0029532120     PISSN: 10518215     EISSN: 15582205     Source Type: Journal    
DOI: 10.1109/76.475890     Document Type: Article

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