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Volumn , Issue , 1995, Pages 196-201
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Quality considerations in delay fault testing
a
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Author keywords
[No Author keywords available]
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Indexed keywords
COMBINATORIAL CIRCUITS;
COMPUTER SIMULATION;
FAILURE ANALYSIS;
LOGIC GATES;
DELAY FAULT TESTING;
DELAY MODELS;
ELECTRICAL-LEVEL SIMULATION;
FAN-OUT GATES;
FAN-OUTS;
LOGIC VALUES/TRANSITIONS;
TEST GENERATION PROCEDURES;
TEST QUALITY;
INTEGRATED CIRCUIT TESTING;
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EID: 0029528194
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (6)
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References (15)
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