Phase edge lithography for sub 0.1 μm electrical channel length in a 200 MM full CMOS process

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1995, Pages 79-80

  Agnello, P ^a   Newman, T ^a   Crabbe, E ^a   Subbanna, S ^a   Ganin, E ^a   Liebemann, L ^a   Comfort, J ^a   Sunderland, D ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRON BEAM LITHOGRAPHY; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; LITHOGRAPHY; MASKS; PHASE SHIFT; X RAY LITHOGRAPHY;

DEEP-ULTRAVIOLET STEPPER; ELECTRICAL CHANNEL LENGTH CONTROL; MID-ULTRAVIOLET LITHOGRAPHY; PHASE EDGE LITHOGRAPHY; PHASE EDGE MASK;

CMOS INTEGRATED CIRCUITS;

EID: 0029520956     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)