Near-Optimal Critical Sink Routing Tree Constructions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 14, Issue 12, 1995, Pages 1417-1436

  Robins, Gabriel ^d  

^a CADENCE DESIGN SYSTEMS   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Nu Mega Technologies ^*  (United States)

^d UNIVERSITY OF VIRGINIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; COMPUTER SIMULATION; CRITICAL PATH ANALYSIS; HEURISTIC METHODS; ITERATIVE METHODS; MATHEMATICAL MODELS; MULTICHIP MODULES; OPTIMIZATION; TREES (MATHEMATICS); VLSI CIRCUITS;

CRITICAL SINK ROUTING TREE; CRITICAL SINK STEINER ALGORITHM; DECOMPOSITION THEOREM; ELMORE DELAY APPROXIMATION; ELMORE ROUTING TREE; GLOBAL SLACK REMOVAL ALGORITHM;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029520879     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.476573     Document Type: Article

References (38)

1. C. J. Alpert, T. C. Hu, J. H. Huang, and A. B. Kahng, “A direct combination of the Prim and Dijkstra constructions for improved performance-driven global routing,” University of California, Los Angeles, Dept. Computer Science, Tech. Rep. CSD-920051, 1992.
2. T. G. Andrews, Ed., Methods of Psychology. New York: Wiley, 1948.
3. B. Awerbuch, A. Baratz, and D. Peleg, “Cost-sensitive analysis of communication protocols,” in Proc. ACM Symp. Principles Distributed Computing, 1990, pp. 177–187.
4. T. Barrera, J. Griffith, G. Robins, and T. Zhang, “Narrowing the gap: Near-optimal Steiner trees in polynomial time,” in Proc. IEEE Int. ASIC Conf., Rochester, NY, Sept. 1993, pp. 87–90.
5. K. D. Boese, J. Cong, A. B. Kahng, K. S. Leung, and D. Zhou, “On high-speed VLSI interconnects: Analysis and design,” in Proc. Asia-Pacific Conf. Circuits Syst,, Sept. 1992, pp. 35–40.
6. K. D. Boese, A. B. Kahng, and G. Robins, “High-performance routing trees with identified critical sinks,” in Proc. ACM/IEEE Design Automat. Conf., June 1993, pp. 182–187.
7. K. D. Boese, A. B. Kahng, B. A. McCoy, and G. Robins, “Fidelity and near-optimality of Elmore-based routing constructions,” in Proc. IEEE Int. Conf. Computer Design, Oct. 1993, pp. 81–84.
8. D.-S. Chen and M. Sarrafzadeh, “A wire-length minimization algorithm for single-layer layouts,” in Proc. IEEE Int. Conf. Computer-Aided Design, 1992, pp. 390–393.
9. J. P. Cohoon and L. J. Randall, “Critical net routing,” Proc. IEEE Int. Conf. Computer Design, 1991, pp. 174–177.
10. J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh, and C. K. Wong, “Provably good performance-driven global routing,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 739–752 June 1992.
11. J. Cong, K.-S. Leung and D. Zhou, “Performance-driven interconnect design based on distributed RC delay model,” in Proc. ACM/IEEE Design Automat. Conf., 1993, pp. 606–611.
12. E. W. Dijkstra, “A note on two problems in connection with graphs,” Numerische Mathematik, vol. 1, pp. 269–271, 1959.
13. W. E. Donath, et al., “Timing driven placement using complete path delays,” in Proc. ACM/IEEE Design Automat. Conf., 1990, pp. 84–89.
14. A. E. Dunlop, V. D. Agrawal, D. N. Deutsh, M. F. Jukl, P. Kozak, and M. Wiesel, “Chip layout optimization using critical path weighting,” in Proc. ACM/IEEE Design Automat. Conf., 1984, pp. 133–136.
15. W. C. Elmore, “The transient response of damped linear network with particular regard to wideband amplifiers,” J. Appl. Phys., vol. 19, pp. 55–63, 1948.
16. S. Even, Graph Algorithms. Potomac, MD: Computer Science, 1979.
17. M. Hanan, “On Steiner's problem with rectilinear distance,” SIAM J. Appl. Math., vol. 14, pp. 255–265, 1966.
18. P. S. Hauge, R. Nair, and E. J. Yoffa, “Circuit placement for predictable performance,” in Proc. IEEE Int. Conf. Computer-Aided Design, 1987, pp. 88–91.
19. J.-M. Ho, G. Vijayan, and C. K. Wong, “New algorithms for the rectilinear Steiner tree problem,” IEEE Trans. Computer-Aided Design, vol. 9, no. 2, pp. 185–193, 1990.
20. M. A. B. Jackson and E. S. Kuh, “Estimating and optimizing RC interconnect delay during physical design,” in Proc. IEEE Int. Conf. Circuits Syst., 1990, pp. 869–871.
21. M. A. B. Jackson, E. S. Kuh, and M. Marek-Sadowska, “Timing-driven routing for building block layout,” in Proc. IEEE Int. Symp. Circuits Syst., pp. 518–519, 1987.
22. A. B. Kahng and G. Robins, “A new class of iterative Steiner tree heuristics with good performance,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 893–902, July 1992.
23. S. Khuller, B. Raghavachari, and N. Young, “Balancing minimum spanning and shortest path trees,” Proc. ACM/SIAM Symp. Discrete Algorithms, to appear.
24. S. Kim, R. M. Owens, and M. J. Irwin, “Experiments with a performance driven module generator,” in Proc. ACM/IEEE Design Automat, Conf., 1992, pp. 687–690.
25. T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout. Berlin: Wiley-Teubner, 1990.
26. I. Lin and D. H. C. Du, “Performance-driven constructive placement,” in Proc. ACM/IEEE Design Automat. Conf., 1990, pp. 103–106.
27. M. Marek-Sadowska and S. Lin, “Timing driven placement,” in Proc. IEEE Int. Conf. Computer-Aided Design, 1989, pp. 94–97.
28. S. Prasitjutrakul and W. J. Kubitz, “A timing-driven global router for custom chip design,” in Proc. IEEE Int. Conf. Computer-Aided Design, 1990, pp. 48–51.
29. A. Prim, “Shortest connecting networks and some generalizations,” Bell Syst. Tech. J., vol. 36, pp. 1389–1401, 1957.
30. S. K. Rao, P. Sadayappan, F. K. Hwang, and P. W. Shor, “The rectilinear Steiner arborescence problem,” Algorithmica, vol. 7, pp. 277–288, 1992.
31. G. Robins, “On optimal interconnections,” Ph.D. dissertation, Dept. Computer Science,, Univ. California, Los Angeles, June 1992.
32. J. Rubinstein, P. Penfield, and M. A. Horowitz, “Signal delay in RC tree networks,” IEEE Trans. Computer-Aided Design, vol. CAD–2, no. 3, pp. 202–211, 1983.
33. A. Srinivasan, K. Chaudhary, and E. S. Kuh, “RITUAL: A performance driven placement algorithm for small-cell IC's,” in Proc. IEEE Int. Conf. Computer-Aided Design, 1991, pp. 48–51.
34. S. Sutanthavibul and E. Shragowitz, “Adaptive timing-driven layout for high speed VLSI,” in Proc. ACM/IEEE Design Automat. Conf., 1990, pp. 90–95.
35. S. Teig, R. L. Smith, and J. Seaton, “Timing driven layout of cell-based IC's,” VLSI Syst. Design, May 1986, pp. 63–73.
36. R. S. Tsay, “Exact zero skew,” in Proc. IEEE Int. Conf. Computer-Aided Design, 1991, pp. 336–339.
37. D. Zhou, F. P. Preparata, and S. M. Kang, “Interconnection delay in very high-speed VLSI,” IEEE Trans. Circuits Syst., vol. 38, July 1991.
38. D. Zhou, S. Su, F. Tsui, D. S. Gao, and J. Cong, “Analysis of trees of transmission lines,” Univ. California, Los Angeles, Tech. Rep. CSD-920010, 1992.