Analytical threshold voltage model for short channel N+ - P+ double-gate SOI MOSFETS

IEEE International SOI Conference

Volumn , Issue , 1995, Pages 68-69

  Suzuki, Kunihiro ^a   Tosaka, Yoshiharu ^a   Sugii, Toshihiro ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRON TUNNELING; GATES (TRANSISTOR); MOSFET DEVICES; NUMERICAL METHODS; SEMICONDUCTOR DOPING; SEMICONDUCTOR SWITCHES; SILICON ON INSULATOR TECHNOLOGY;

DOPING CONCENTRATION; GATE LENGTH; SEMICONDUCTOR DEVICE DESIGN; SHORT CHANNEL EFFECTS; THRESHOLD VOLTAGE MODEL;

SEMICONDUCTOR DEVICE MODELS;

EID: 0029520439     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)