Test point insertion for an area efficient BIST

IEEE International Test Conference (TC)

Volumn , Issue , 1995, Pages 515-523

  Schotten, Claus ^a   Meyr, Heinrich ^a  

^a RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; CRITICAL PATH ANALYSIS; ELECTRIC NETWORK ANALYSIS; ERROR DETECTION; FEEDBACK; LOGIC DESIGN; RANDOM PROCESSES;

BUILT-IN SELF TEST SCHEME; DESIGN FOR TESTABILITY; GATE LEVEL NETLIST; PSEUDORANDOM PATTERNS; TEST POINT INSERTION; TESTABILITY ANALYSIS;

SEQUENTIAL CIRCUITS;

EID: 0029517976     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)