Intra-die device parameter variations and their impact on digital CMOS gates at low supply voltages

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1995, Pages 67-70

  Eisele, M ^a   Berthold, J ^a   Thewes, R ^a   Wohlrab, E ^a   Schmitt Landsiedel, D ^a   Weber, W ^a  

^a SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC INVERTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); MOSFET DEVICES; PARAMETER ESTIMATION; STATISTICAL METHODS; VOLTAGE CONTROL; VOLTMETERS;

CHANNEL DOPING VARIATIONS; DIGITAL CMOS GATES; INTRA-DIE DEVICE PARAMETER VARIATIONS; INVERTER DELAYS; LOW SUPPLY VOLTAGES;

CMOS INTEGRATED CIRCUITS;

EID: 0029516202     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)