-
1
-
-
0022027064
-
Design tradeoffs between surface and buried-channel FET's
-
G. J. Hu and R. H. Bruce, “Design tradeoffs between surface and buried-channel FET's,” IEEE Trans. Electron Devices, vol. ED-32, p. 584, 1985.
-
(1985)
IEEE Trans.Devices Electron
, vol.ED-32
, pp. 584
-
-
Hu, G.J.1
Bruce, R.H.2
-
2
-
-
0023604110
-
Design methodology for deep submicron CMOS
-
K. Tanaka and M. Fukuma, “Design methodology for deep submicron CMOS,” in IEDM Tech. Dig., p. 628, 1987.
-
(1987)
IEDM Tech. Dig.
, pp. 628
-
-
Tanaka, K.1
Fukuma, M.2
-
3
-
-
0025448697
-
Analysis of hot-carrier-induced degradation mode on pMOSFET's
-
F. Matsuoka, H. Iwai, H. Hayashida, K. Hama, Y. Toyoshima and K. Maeguchi, “Analysis of hot-carrier-induced degradation mode on pMOSFET's,” IEEE Trans. Electron Devices, vol. 37, p. 1487, 1990.
-
(1990)
IEEE Trans. Electron Devices
, vol.37
, pp. 1487
-
-
Matsuoka, F.1
Iwai, H.2
Hayashida, H.3
Hama, K.4
Toyoshima, Y.5
Maeguchi, K.6
-
4
-
-
0023120271
-
Submicrometer-channel CMOS for low-temperature operation
-
J. Y.-C. Sun, Y. Taur, R. H. Dennard, and •S. P. Klepner, “Submicrometer-channel CMOS for low-temperature operation,” IEEE Trans. Electron Devices, vol. ED-34, p. 19, 1987.
-
(1987)
IEEE Trans. Electron Devices
, vol.ED-34
, pp. 19
-
-
Sun, J.Y.-C.1
Taur, Y.2
Dennard, R.H.3
Klepner, S.P.4
-
5
-
-
0024930239
-
Study of boron penetration through thin oxide with p+ -polysilicon gate
-
J. Y.-C. Sun, C. Wong, Y. Taur, and C.-H. Hsu, “Study of boron penetration through thin oxide with p+ -polysilicon gate,” in Proc. 1989 Symp. VLSI Technol. 1989, p. 17.
-
(1989)
Proc.1989 Symp. VLSI Technol
, pp. 17.
-
-
Sun, J. Y.-C.1
Wong, C.2
Taur, Y.3
Hsu, C.-H.4
-
6
-
-
0025474417
-
The effects of boron penetration on p+ polysilicon gated PMOS devices
-
J. R. Pfiester, F. K. Baker, T. C. Mele, H.-H. Tseng, P. J. Tobin, J. D. Hayden, J. W. Miller, C. D. Gunderson, and L. C. Parrillo, “The effects of boron penetration on p+ polysilicon gated PMOS devices,” IEEE Trans. Electron Devices, vol. 37, p. 1842, 1990.
-
(1990)
IEEE Trans. Electron Devices
, vol.37
, pp. 1842
-
-
Pfiester, J.R.1
Baker, F.K.2
Mele, T.C.3
Tseng, H.-H.4
Tobin, P.J.5
Hayden, J.D.6
Miller, J.W.7
Gunderson, C.D.8
Parrillo, L.C.9
-
7
-
-
0025522695
-
A comprehensive study on p+ polysilicon-gate MOSFET's instability with fluorine incorporation
-
J. J. Sung and C.-Y. Lu, “A comprehensive study on p+ polysilicon-gate MOSFET's instability with fluorine incorporation,” IEEE Trans. Electron Devices, vol. 37, p. 2312, 1990.
-
(1990)
IEEE Trans. Electron Devices
, vol.37
, pp. 2312
-
-
Sung, J.J.1
Lu, C.-Y.2
-
8
-
-
0028544537
-
Anomalous reverse short-channel effect in p+ polysilicon gated P-channel MOSFET
-
C.-Y. Chang, C.-Y. Lin, J. W. Chou, C. C.-H. Hsu, H.-T. Pan, and J. Ko, “Anomalous reverse short-channel effect in p+ polysilicon gated P-channel MOSFET,” IEEE Electron Device Lett., vol. 15, no. 11, pp. 437-439, 1994.
-
(1994)
IEEE Electron Device Lett.
, vol.15
, Issue.11
, pp. 437-439
-
-
Chang, C.-Y.1
Lin, C.-Y.2
Chou, J.W.3
Hsu, C.C.-H.4
Pan, H.-T.5
Ko, J.6
-
9
-
-
1642636654
-
Redistribution of acceptor and donor impurities during thermal oxidation of silicon
-
A. S. Grove, O. Leistiko, Jr., and C. T. Sah, “Redistribution of acceptor and donor impurities during thermal oxidation of silicon,” J. Appl. Phys., vol. 35, p. 2695, 1964.
-
(1964)
J. Appl. Phys.
, vol.35
, pp. 2695
-
-
Grove, A.S.1
Leistiko, O.2
Sah, C.T.3
-
10
-
-
0038416243
-
Ambient and dopant effects on boron diffusion in oxides
-
C. Y. Wong and F. S. Lai, “Ambient and dopant effects on boron diffusion in oxides,” Appl. Phys. Lett., vol. 48, p. 1658, 1986.
-
(1986)
Appl. Phys. Lett.
, vol.48
, pp. 1658
-
-
Wong, C.Y.1
Lai, F.S.2
-
11
-
-
0023559765
-
Very thin nitride/oxide composite gate insulator for VLSI CMOS
-
L. Dori, J. Sun, M. Arienzo, S. Basavaiah, Y. Taur, and D. Zichermann, “Very thin nitride/oxide composite gate insulator for VLSI CMOS,” in Symp. VLSI Technol., 1987, p. 25.
-
(1987)
Symp. VLSI Technol.
, pp. 25.
-
-
Dori, L.1
Sun, J.2
Arienzo, M.3
Basavaiah, S.4
Taur, Y.5
Zichermann, D.6
-
12
-
-
0025578297
-
Electrical and reliability characteristics of ultrathin oxynitride gate dielectric prepared by rapid thermal processing in N2O
-
H. Hwang, W. Ting, D.-L. Kwong, and J. Lee, “Electrical and reliability characteristics of ultrathin oxynitride gate dielectric prepared by rapid thermal processing in N2O,” in IEDM Tech. Dig., 1990, p. 421.
-
(1990)
IEDM Tech. Dig.
, pp. 421.
-
-
Hwang, H.1
Ting, W.2
Kwong, D.-L.3
Lee, J.4
-
13
-
-
0025577946
-
High performance dual-gate sub-halfmicron CMOSFET's with 6 nm-thick nitrided SiO2 films in an N2O ambient
-
A. Uchiyama, H. Fukuda, T. Hayashi, T. Iwabuchi and S. Ohno, “High performance dual-gate sub-halfmicron CMOSFET's with 6 nm-thick nitrided SiO2 films in an N2O ambient,” in IEDM Tech. Dig., 1990, p. 425.
-
(1990)
IEDM Tech. Dig.
, pp. 425.
-
-
Uchiyama, A.1
Fukuda, H.2
Hayashi, T.3
Iwabuchi, T.4
Ohno, S.5
-
14
-
-
0025577329
-
Effects of boron penetration and resultant limitations in ultra thin pure-oxide and nitrided-oxide gate-films
-
T. Morimoto, H. S. Momose, Y. Ozawa, K. Yamabe, and H. Iwai, “Effects of boron penetration and resultant limitations i n ultra thin pure-oxide and nitrided-oxide gate-films,” in IEDM Tech. Dig., 1990, p. 429.
-
(1990)
IEDM Tech. Dig.
, pp. 429.
-
-
Morimoto, T.1
Momose, H.S.2
Ozawa, Y.3
Yamabe, K.4
Iwai, H.5
-
15
-
-
0026117813
-
Impurity barrier properties of reoxidized nitrided oxide films for use with p+ -doped polysilicon gates
-
J. S. Cable, R. A. Mann, and J. C. S. Woo, “Impurity barrier properties of reoxidized nitrided oxide films for use with p+ -doped polysilicon gates,” IEEE Electron Device Lett., vol. 12, p. 128, 1991.
-
(1991)
IEEE Electron Device Lett.
, vol.12
, pp. 128
-
-
Cable, J.S.1
Mann, R.A.2
Woo, J.C.S.3
-
16
-
-
0026141859
-
The use of ultrathin reoxidized nitrided gate oxide for suppression of boron penetration in BF2+ -implanted polysilicon gated p-MOSFET's
-
G. Q. Lo and D.-L. Kwong, “The use of ultrathin reoxidized nitrided gate oxide for suppression of boron penetration in BF2+ -implanted polysilicon gated p-MOSFET's,” IEEE Electron Device Lett., vol. 12, p. 175, 1991.
-
(1991)
IEEE Electron Device Lett.
, vol.12
, pp. 175
-
-
Lo, G.Q.1
Kwong, D.-L.2
-
17
-
-
84954184836
-
Very lightly nitrided oxide gate MOSFET's for deep-sub-micron CMOS devices
-
H. S. Momose, T. Morimoto, Y. Ozawa, M. Tsuchiaki, M. Ono, K. Yamabe, and H. Iwai, “Very lightly nitrided oxide gate MOSFET's for deep-sub-micron CMOS devices,” in IEDM Tech. Dig., 1991, p. 359.
-
(1991)
IEDM Tech. Dig.
, pp. 359.
-
-
Momose, H.S.1
Morimoto, T.2
Ozawa, Y.3
Tsuchiaki, M.4
Ono, M.5
Yamabe, K.6
Iwai, H.7
-
18
-
-
0026853303
-
Low-temperature furnace-grown reoxidized nitrided oxide gate dielectrics as a barrier to boron penetration
-
H. Fang, K. S. Krisch, B. J. Gross, C. G. Sodini, J. Chung, and D. A. Antoniadis, “Low-temperature furnace-grown reoxidized nitrided oxide gate dielectrics as a barrier to boron penetration,” IEEE Electron Device Lett., vol. 13, p. 217, 1992.
-
(1992)
IEEE Electron Device Lett.
, vol.13
, pp. 217
-
-
Fang, H.1
Krisch, K.S.2
Gross, B.J.3
Sodini, C.G.4
Chung, J.5
Antoniadis, D.A.6
-
19
-
-
0027841017
-
Oxynitride gate dielectrics for p+ -polysilicon gate MOS devices
-
A. B. Joshi, J. Ahn, and D. L. Kwong, “Oxynitride gate dielectrics for p+ -polysilicon gate MOS devices,” IEEE Electron Device Lett., vol. 14, p. 560, 1993.
-
(1993)
IEEE Electron Device Lett.
, vol.14
, pp. 560
-
-
Joshi, A.B.1
Ahn, J.2
Kwong, D.L.3
-
20
-
-
0028383350
-
Suppression of Boron penetration in P+ polysilicon gate P-MOSFET's using low-temperature gate-oxide N2O anneal
-
Z. J. Ma, J. C. Chen, Z. H. Liu, J. T. Krick, Y. C. Cheng, C. Hu, and P. K. Ko, “Suppression of Boron penetration in P+ polysilicon gate P-MOSFET's using low-temperature gate-oxide N2O anneal,” IEEE Electron Device Lett., vol. 15, p. 109, 1994.
-
(1994)
IEEE Electron Device Lett.
, vol.15
, pp. 109
-
-
Ma, Z.J.1
Chen, J.C.2
Liu, Z.H.3
Krick, J.T.4
Cheng, Y.C.5
Hu, C.6
Ko, P.K.7
-
21
-
-
0026897882
-
The effect of silicon gate microstructure, and gate oxide process on threshold voltage instabilities in p+ -gate p-channel MOSFET's with fluorine incorporation
-
H.-H. Tseng, P. J. Tobin, F. K. Baker, J. R. Pfiester, R. Evans, and P. L. Fejes, “The effect of silicon gate microstructure, and gate oxide process on threshold voltage instabilities in p+ -gate p-channel MOSFET's with fluorine incorporation,” IEEE Trans. Electron Devices, vol. ED-39, p. 1687, 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.ED-39
, pp. 1687
-
-
Tseng, H.-H.1
Tobin, P.J.2
Baker, F.K.3
Pfiester, J.R.4
Evans, R.5
Fejes, P.L.6
-
22
-
-
0027879329
-
Suppression of boron penetration into an ultra-thin gate oxide (<7 nm) by using a stacked-amorphous-silicon (SAS) film
-
S. L. Wu, C. L. Lee, and T. F. Lei, “Suppression of boron penetration into an ultra-thin gate oxide (<7 nm) by using a stacked-amorphous-silicon (SAS) film,” in IEDM Tech. Dig., 1993, p. 329.
-
(1993)
IEDM Tech. Dig.
, pp. 329.
-
-
Wu, S.L.1
Lee, C.L.2
Lei, T.F.3
-
23
-
-
0027867599
-
Improving gate oxide integrity in p+ pMOSFET by using large grain size po1ysilicon gate
-
M. Koda, Y. Shida, J. Kawaguchi and Y. Kaneko, “Improving gate oxide integrity in p+ pMOSFET by using large grain size po1ysilicon gate,” in IEDM Tech. Dig., 1993, p. 471.
-
(1993)
IEDM Tech. Dig.
, pp. 471.
-
-
Koda, M.1
Shida, Y.2
Kawaguchi, J.3
Kaneko, Y.4
-
24
-
-
84954153094
-
p+ polysilicon gate P-MOSFET's using BCL implantation
-
K. Oikawa, S. Ando, N. Ando, H. Horie, Y. Toda, T. Tanaka, and S. Hijiya, “p+ polysilicon gate P-MOSFET's using BCL implantation,” in IEDM Tech. Dig., 1991, p. 79.
-
(1991)
IEDM Tech. Dig.
, pp. 79.
-
-
Oikawa, K.1
Ando, S.2
Ando, N.3
Horie, H.4
Toda, Y.5
Tanaka, T.6
Hijiya, S.7
-
25
-
-
0029358561
-
Suppression of boron penetration in BF2 -implanted P-type gate MOSFET by trapping of fluorines in amorphous gate
-
Aug.
-
C.-Y. Lin, C.-Y. Chang, and C. C.-H. Hsu, “Suppression of boron penetration in BF2 -implanted P-type gate MOSFET by trapping of fluorines in amorphous gate,” IEEE Trans. Electron Devices, vol. 42, no. 8, pp. 1503–1509, Aug. 1995.
-
(1995)
IEEE Trans. Electron Devices
, vol.42
, Issue.8
, pp. 1503-1509
-
-
Lin, C.-Y.1
Chang, C.-Y.2
Hsu, C.C.-H.3
-
26
-
-
0021375812
-
Capture and tunnel emission of electrons by deep levels in ultrathin nitrided oxides on silicon
-
S. T. Chang, N. M. Johnson, and S. A. Lyon, “Capture and tunnel emission of electrons by deep levels in ultrathin nitrided oxides on silicon,” Appl. Phys. Lett., vol. 44, p. 316, 1984.
-
(1984)
Appl. Phys. Lett.
, vol.44
, pp. 316
-
-
Chang, S.T.1
Johnson, N.M.2
Lyon, S.A.3
-
27
-
-
0021409073
-
Study of electrical characteristics on thermally nitrided SiO2 (nitroxide) films
-
C. T. Chen, F. C. Tseng, C. Y. Chang, and M. K. Lee, “Study of electrical characteristics on thermally nitrided SiO2 (nitroxide) films,” J. Electrochem. Soc., vol. 131, p. 875, 1984.
-
(1984)
J. Electrochem. Soc.
, vol.131
, pp. 875
-
-
Chen, C.T.1
Tseng, F.C.2
Chang, C.Y.3
Lee, M.K.4
-
28
-
-
0024048525
-
Optimization of low-pressure nitridation/reoxidation of SiO2 for scaled MOS devices
-
W. Yang, R. Jayararnan, and C. G. Sodini, “Optimization of low-pressure nitridation/reoxidation of SiO2 for scaled MOS devices,” IEEE Trans. Electron Devices, vol. 35, p. 935, 1988.
-
(1988)
IEEE Trans. Electron Devices
, vol.35
, pp. 935
-
-
Yang, W.1
Jayararnan, R.2
Sodini, C.G.3
-
29
-
-
84963760109
-
Nonequilibrium effects in quasistatic MOS measurements
-
M. Kuhn and E. H. Nicollian, “Nonequilibrium effects in quasistatic MOS measurements,” J. Electrochem. Soc., vol. 118, p. 370, 1971.
-
(1971)
J. Electrochem. Soc.
, vol.118
, pp. 370
-
-
Kuhn, M.1
Nicollian, E.H.2
-
30
-
-
0028416619
-
Electrical characteristics of rapid thermal nitrided-oxide gate n- and p-MOSFET's with less than 1 atom nitrogen concentration
-
H. S. Momose, T. Morimoto, Y. Ozawa, K. Yamabe, and H. Iwai, “Electrical characteristics of rapid thermal nitrided-oxide gate n- and p-MOSFET's with less than 1 atom nitrogen concentration,” IEEE Trans. Electron Devices, vol. 41, p. 546, 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, pp. 546
-
-
Momose, H.S.1
Morimoto, T.2
Ozawa, Y.3
Yamabe, K.4
Iwai, H.5
-
31
-
-
0028484275
-
Optimization of gate oxide N2O anneal for CMOSFET's at room and cryogenic temperatures
-
Z.-J. Ma, Z. H. Liu, J. T. Krick, H. J. Huang, Y. C. Cheng, C. Hu, and P. K. Ko, “Optimization of gate oxide N2O anneal for CMOSFET's at room and cryogenic temperatures,” IEEE Trans. Electron Devices, vol. 41, p. 1364, 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, pp. 1364
-
-
Ma, Z.-J.1
Liu, Z.H.2
Krick, J.T.3
Huang, H.J.4
Cheng, Y.C.5
Hu, C.6
Ko, P.K.7
-
32
-
-
0027627558
-
Evaluation of Qbd for electrons tunneling from the Si/SiO2 interface compared to electron tunneling from the Poly-Si/SiO2 interface
-
S. S. Gong, M. E. Burnham, N. D. Theodore, and D. K. Schroder, “Evaluation of Qbd for electrons tunneling from the Si/SiO2 interface compared to electron tunneling from the Poly-Si/SiO2 interface,” IEEE Trans. Electron Devices, vol. 40, p. 1251, 1993.
-
(1993)
IEEE Trans. Electron Devices
, vol.40
, pp. 1251
-
-
Gong, S.S.1
Burnham, M.E.2
Theodore, N.D.3
Schroder, D.K.4
-
33
-
-
0024663207
-
The effect of fluorine in silicon dioxide gate dielectrics
-
P.J. Wright and K. C. Saraswat, “The effect of fluorine in silicon dioxide gate dielectrics,” IEEE Trans. Electron Devices, vol. 36, p. 879, 1989.
-
(1989)
IEEE Trans. Electron Devices
, vol.36
, pp. 879
-
-
Wright, P.J.1
Saraswat, K.C.2
-
34
-
-
0025419055
-
Oxygen concentration in LPCVD polysilicon films
-
Apr.
-
T. I. Kamins and J. E. Turner, “Oxygen concentration in LPCVD polysilicon films,” Solid-State Technol., p. 80, Apr. 1990.
-
(1990)
Solid-State Technol.
, pp. 80
-
-
Kamins, T.I.1
Turner, J.E.2
-
35
-
-
0026712574
-
Fluorine diffusion on a polysilicon grain boundary network in relation to boron penetration from p+ gates
-
H.-H. Tseng, M. Orlowski, P. J. Tobin, and R. L. Hance, “Fluorine diffusion on a polysilicon grain boundary network in relation to boron penetration from p+ gates,” IEEE Electron Device Lett., vol. 13, p. 14, 1992.
-
(1992)
IEEE Electron Device Lett.
, vol.13
, pp. 14
-
-
Tseng, H.-H.1
Orlowski, M.2
Tobin, P.J.3
Hance, R.L.4
-
36
-
-
0029346202
-
Effect of oxygen impurity on microstructure and boron penetration in a BF2+ implanted LPCVD stacked amorphous silicon p+ gated PMOS capacitor
-
C.-Y. Lin, F.-M. Pan, P.-F. Chou, and C.-Y. Chang, “Effect of oxygen impurity on microstructure and boron penetration in a BF2+ implanted LPCVD stacked amorphous silicon p+ gated PMOS capacitor,” J. Electrochem. Soc., vol. 143, p. 2434, 1995.
-
(1995)
J. Electrochem. Soc.
, vol.143
, pp. 2434
-
-
Lin, C.-Y.1
Pan, F.-M.2
Chou, P.-F.3
Chang, C.-Y.4
|