Integration of IEEE Std. 1149.1 and mixed-signal test architectures

IEEE International Test Conference (TC)

Volumn , Issue , 1995, Pages 569-576

  Cheek, David J ^a   Dandapani, R ^a  

^a UNIVERSITY OF COLORADO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; SHIFT REGISTERS; SWITCHING NETWORKS;

BOUNDARY SCAN REGISTER CELLS; CORE DISCONNECT SWITCH; EFFECTIVENESS; MIXED SIGNAL TEST ARCHITECTURES; MIXED SIGNAL TESTING; TESTABILITY BUS STRUCTURE;

COMPUTER ARCHITECTURE;

EID: 0029514412     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)