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Volumn , Issue , 1995, Pages 203-208
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Pin assignment and routing on a single-layer pin grid array
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Author keywords
[No Author keywords available]
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Indexed keywords
DIGITAL ARITHMETIC;
ELECTRIC WIRE;
ELECTRIC WIRING;
ELECTRONICS PACKAGING;
GEOMETRY;
INTEGRATED CIRCUIT LAYOUT;
ITERATIVE METHODS;
MATHEMATICAL TRANSFORMATIONS;
THEOREM PROVING;
TOPOLOGY;
MONOTONIC TOPOLOGICAL ROUTING;
PIN ASSIGNMENT;
PIN GRID ARRAY;
ROUTING;
ALGORITHMS;
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EID: 0029514262
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (24)
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References (9)
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