New degradation mode of scaled p+ polysilicon gate pMOSFETs induced by bias temperature (BT) instability

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1995, Pages 871-874

  Uwasawa, Ken'ichi ^a   Yamamoto, Toyoji ^a   Mogami, Tohru ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; DEFECTS; DEGRADATION; GATES (TRANSISTOR); ION IMPLANTATION; LEAKAGE CURRENTS; OXIDES; SEMICONDUCTING BORON; SEMICONDUCTING SILICON;

BIAS TEMPERATURE INSTABILITY; BIAS TEMPERATURE STRESS; BORON PENETRATION; CHARGE PUMPING METHOD; DIFFUSION CONTROLLED ELECTROCHEMICAL REACTION; FURNACE ANNEALING; INTERFACE STATE DENSITY;

MOSFET DEVICES;

EID: 0029513628     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)