Delay model for logic synthesis of continuously-sized networks

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1995, Pages 458-462

  Grodstein, Joel ^a   Lehman, Eric ^a   Harkness, Heather ^a   Grundmann, Bill ^a   Watanabe, Yosinatori ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK SYNTHESIS; LOGIC CIRCUITS; MATHEMATICAL MODELS; TREES (MATHEMATICS);

CONTINUOUSLY SIZED NETWORKS; DELAY MODEL; LOGIC SYNTHESIS;

LOGIC DESIGN;

EID: 0029513451     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)