An analytical drain current model for short-channel fully-depleted ultrathin silicon-on-insulator NMOS devices

Solid State Electronics

Volumn 38, Issue 12, 1995, Pages 2051-2057

  Chen, Y G ^a   Kuo, J B ^a   Yu, Z ^b   Dutton, R W ^b  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CRYSTAL LATTICES; ELECTRIC CURRENTS; ELECTRIC FIELDS; GATES (TRANSISTOR); IONIZATION; NUMERICAL ANALYSIS; SEMICONDUCTOR DEVICE MODELS; SILICON ON INSULATOR TECHNOLOGY; THERMAL EFFECTS; THIN FILMS;

ANALYTICAL DRAIN CURRENT MODEL; ELECTRON MOBILITY; ENERGY BALANCE EQUATION; LATTICE THERMAL EFFECT; PARASITIC EFFECT; SILICON ON INSULATOR NMOS DEVICES;

MOS DEVICES;

EID: 0029510727     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/0038-1101(95)00083-6     Document Type: Article

References (16)

1. VIA-4 avalanche-induced breakdown mechanisms in short-channel MOSFETs
2. Detailed characterization and analysis of the breakdown voltage in fully depleted SOI n-MOSFET's
3. Negative dynamic resistance in MOS devices
4. A simple two-dimensional model for IGFET operation in the saturation region