3-Gb/s CMOS 1:4 MUX and DEMUX ICs

IEICE Transactions on Electronics

Volumn E78-C, Issue 12, 1995, Pages 1746-1753

  Yasuda, Sadayuki ^a   Ohtomo, Yusuke ^a   Ino, Masayuki ^a   Kado, Yuichi ^a   Tsuchiya, Toshiaki ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; LOGIC DESIGN; MULTIPLEXING EQUIPMENT;

DEMULTIPLEXER; DOUBLE RAIL FLIP FLOP; INTERNAL MEAN CAPACITANCE;

CMOS INTEGRATED CIRCUITS;

EID: 0029504902     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (7)