Timing analysis models for gates and cells with bipolar-transistor output stages

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 1995, Pages 149-152

  Tesu, Ion Constantin ^a   Pileggi, Lawrence T ^a  

^a GHEORGHE ASACHI TECHNICAL UNIVERSITY OF IASI   (Romania)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC IMPEDANCE; EMITTER COUPLED LOGIC CIRCUITS; MATHEMATICAL MODELS; OSCILLATIONS; TRANSIENTS; WAVEFORM ANALYSIS;

INTERCONNECT RESPONSE WAVEFORMS; ORDER REDUCTION METHOD; TIMING ANALYSIS; TRANSIENT RESPONSE;

LOGIC GATES;

EID: 0029503495     PISSN: 10630988     EISSN: None     Source Type: None    
DOI: 10.1109/ASIC.1995.580702     Document Type: Conference Paper

References (10)