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Volumn , Issue , 1995, Pages 400-405
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Use of embedded scheduling to compile VHDL for effective parallel simulation
a
a
IBM
(United States)
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Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
CODES (SYMBOLS);
COMPUTATIONAL LINGUISTICS;
COMPUTER SIMULATION;
DISTRIBUTED COMPUTER SYSTEMS;
PARALLEL PROCESSING SYSTEMS;
PROGRAM COMPILERS;
PROGRAM PROCESSORS;
RESPONSE TIME (COMPUTER SYSTEMS);
SCHEDULING;
AURIGA COMPILER;
COMPILE-TIME;
DISCRETE EVENT SIMULATION ALGORITHM;
MESSAGE-BASED COMPUTERS;
PERFORMANCE MEASUREMENTS;
RUN-TIME ALGORITHMS;
SCHEDULER;
STATIC PROCESS GRAPH;
TEMPORAL SEMANTICS;
VHDL COMPILATION;
COMPUTER HARDWARE DESCRIPTION LANGUAGES;
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EID: 0029503205
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (4)
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References (16)
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