Scalable systolic array architecture for 2-D discrete wavelet transforms

IEEE Workshop on VLSI Signal Processing, Proceedings

Volumn , Issue , 1995, Pages 303-312

  Chen, Jijun ^a   Bayoumi, Magdy A ^a  

^a UNIVERSITY OF LOUISIANA AT LAFAYETTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; IMAGE CODING; IMAGE COMPRESSION; INTEGRATED CIRCUIT LAYOUT; VLSI CIRCUITS; WAVELET TRANSFORMS;

DATA DEPENDENCE ANALYSIS; DISCRETE WAVELET TRANSFORMS; LINEAR INDEX SPACE TRANSFORMATION; SCALABLE SYSTOLIC ARRAY ARCHITECTURE;

SYSTOLIC ARRAYS;

EID: 0029502109     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)