A 2 V, 10 b, 20 Msample/s, Mixed-Mode Subranging CMOS A/D Converter

IEEE Journal of Solid-State Circuits

Volumn 30, Issue 12, 1995, Pages 1533-1537

  Yotsuyanagi, Michio ^a   Hasegawa, Hiroshi ^a   Yamaguchi, Motoi ^a   Ishida, Masaki ^a   Sone, Kazuya ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; ELECTRIC CURRENTS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER SUPPLIES TO APPARATUS; ERROR CORRECTION; IMAGE COMMUNICATION SYSTEMS; INTEGRATED CIRCUIT LAYOUT;

CMOS ANALOG TO DIGITAL CONVERTERS; DIFFERENTIAL COMPARATORS; MIXED MODE SUBRANGING; VOLTAGE MODE CIRCUITRY; VOLTAGE TO CURRENT CONVERTERS;

ELECTRIC CONVERTERS;

EID: 0029488307     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.482202     Document Type: Article

References (7)

1. T. Cho and P. Gray, “A 10 bit 20 MS/s, 35 mW pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 30, pp. 166–172, Mar. 1995.
2. K. Nakamura et al., “A 85 mW 10 bit 40 MS/s ADC with decimated parallel architecture,” IEEE J. Solid-State Circuits, vol. 30, pp. 173–183, Mar. 1995.
3. N. Kumazawa, “A CMOS 3 V 24 mW 20 MSPS 10 bit A/D converter with self calibration unit,” in Symp. VLSI Circuits Dig. Tech. Papers, June 1994, pp. 15–16.
4. K. Kusumoto et al., “A 10 b 20 MHz 30 mW pipelined interpolating CMOS ADC,” IEEE J. Solid-State Circuits, vol. 28, pp. 1200–1206, Dec. 1993.
5. M. Ito et al., “A 10 b 20 MS/s 3 V-supply CMOS A/D converter,” IEEE J. Solid-State Circuits, vol. 29, pp. 1531–1536, Dec. 1994.
6. H. Hasegawa et al., “A 1.5 V video-speed current-mode current-tree A/D converter,” in Symp. VLSI Circuits Dig. Tech. Papers, June 1994, pp. 17–18.
7. M. Yotsuyanagi, “A 10 b 50 MHz pipelined CMOS A/D converter with S/H,” IEEE J. Solid-State Circuits, vol. 28, pp. 292–300, Mar. 1993.