Challenges raised by long on-chip wiring for CMOS microprocessor applications

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 1995, Pages 21-23

  Deutsch, A ^a   Kopcsay, G V ^a   Surovic, C W ^a   Rubin, B J ^a   Terman, L M ^a   Dunne, R P ^a   Gallo, T ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; CROSSTALK; ELECTRIC CONDUCTIVITY; ELECTRIC CONDUCTORS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC RESISTANCE; ELECTRIC WIRING; ELECTRONICS PACKAGING; MICROPROCESSOR CHIPS;

DELAY TOLERANCE; GLOBAL CONNECTIVITY; ON-CHIP WIRING; PACKAGE INTERCONNECTIONS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029486161     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)