A 1.5 V Class AB CMOS Buffer Amplifier for Driving Low-Resistance Loads

IEEE Journal of Solid-State Circuits

Volumn 30, Issue 12, 1995, Pages 1333-1338

  van Dongen, Rob ^a   Rikkink, Vincent ^a  

^a CSEM   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUFFER AMPLIFIERS; CASCADE CONNECTIONS; CIRCUIT THEORY; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENT CONTROL; ELECTRIC DISTORTION; ELECTRIC LOADS; TRANSCONDUCTANCE; TRANSFER FUNCTIONS; TRANSISTORS;

ELEMENTARY SHUNT STAGE; GAIN BANDWIDTH; LOW RESISTANCE LOAD; PRINCIPLE OF OPERATION; QUIESCENT POWER; TRANSCONDUCTOR BLOCK;

OPERATIONAL AMPLIFIERS;

EID: 0029485003     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.482159     Document Type: Article

References (8)

1. W.-C. Wu, W. Helms, J. Kuhn, and B. Byrkett, “Digital-compatible high-performance operational amplifier with rail-to-rail input and output ranges,” IEEE J. Solid-State Circuits, vol. 29, pp. 63–66, Jan. 1994.
2. F. Mistlberger and R. Koch, “Class-AB high-swing CMOS power amplifier,” IEEE J. Solid-State Circuits, vol. 27, pp. 1089–1092, July 1992.
3. F. Op't Eynde, P. Ampe, L. Verdeyen, and W. Sansen, “A CMOS large-swing low-distortion three-stage class AB power amplifier,” IEEE J. Solid-State Circuits, vol. 25, pp. 265–273, Feb. 1990.
4. J. Kih et al., “Class-AB large-swing CMOS buffer amplifier with controlled bias current,” IEEE J. Solid-State Circuits, vol. 28, pp. 1350–1353, Dec. 1993.
5. R. Eschauzier, R. Hogervorst, and J. Huijsing, “A programmable 1.5 V CMOS class-AB opamp with hybrid nested Miller compensation for 120 db gain and 6 MHz UGF,” IEEE J. Solid-State Circuits, vol. 29, pp. 1497–874, Dec. 1994.
6. R. Gregorian and G. Temes, Analog MOS Integrated Circuits for Signal Processing. New York: Wiley, 1986, ch. 4.
7. B. Y. Kamath, R. Meyer, and P. Gray, “Relationship between frequency response and settling time of operational amplifiers,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 347–352, Dec. 1974.
8. P. Duchene et al., “Analog circuit implementation on CMOS semicustom arrays,” IEEE J. Solid-State Circuits, vol. 28, pp. 872–874, July 1993.