Effects of test condition, microstructure and linewidth on electromigration void morphology

Materials Research Society Symposium - Proceedings

Volumn 391, Issue , 1995, Pages 379-384

  Bauguess, S ^a   Dreyer, M L ^a   Tucker, M ^a   Theodore, D ^a   Lee, C T ^a   Edwards, S ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM ALLOYS; CHARACTERIZATION; CURRENT DENSITY; ELECTRIC CONDUCTORS; GRAIN SIZE AND SHAPE; MATERIALS TESTING; METALLIZING; MICROSTRUCTURE; MORPHOLOGY; SUBSTRATES; TRANSMISSION ELECTRON MICROSCOPY; VLSI CIRCUITS; ELECTROMIGRATION; MICROELECTRONICS;

FAILURE TIME DISTRIBUTION; LINEWIDTH; POLYGRAIN; VOID; CURRENT STRESS; FAILURE-TIME DISTRIBUTION; GRAIN SIZE DISTRIBUTION; LINEWIDTH DEPENDENCE; TEMPERATURE STRESS; TEST CONDITION; VOID DISTRIBUTIONS; VOID MORPHOLOGY;

ELECTROMIGRATION; LINEWIDTH;

EID: 0029478533     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1557/proc-391-379     Document Type: Conference Paper

References (13)