Development and synthesis method for pass-transistor logic family for high-speed and low power CMOS

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 1995, Pages 298-301

  Oklobdzija, Vojin G ^a   Soderstrand, Michael ^a   Duchene, Benoit ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOGIC DESIGN; LOGIC GATES; OPTIMIZATION; TRANSISTORS;

DUAL VALUE LOGIC; KARNAUGH MAP; PASS TRANSISTOR LOGIC;

LOGIC CIRCUITS;

EID: 0029452530     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)