Laddering Wave in Serpentine Delay Line

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 18, Issue 4, 1995, Pages 644-650

  Wu, Ruey Beei ^a   Chao, Fang Lin ^b,c  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^c The Da Yeh Institute of Technology ^*  (China)

Author keywords

clock skew; crosstalk; Delay line; signal integrity

Indexed keywords

EID: 0029410586     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.475270     Document Type: Article

References (12)

1. H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990, chap. 8.
2. H. Bakoglu, J. T. Walker, and J. D. Meindl, “A symmetric clock-distribution tree and optimized high-speed interconnections for reduced clock skew in ULSI and WSI circuits,” in Proc. IEEE lnt. Conf. Computer Design, 1986, pp. 118–122.
3. M. A. B. Jackson, A. Srinivasan, and E. S. Kuh, “Clock routing for high performance IC’s,” in Proc. ACM/IEEE Design Automation Conf., 1990, p p. 573–579.
4. A. B. Kahng, J. Cong, and G. Robins, “High-performance clock routing based on recursive geometric matching,” in Proc. ACM/IEEE Design Automation Conf., 1991, pp. 322–327.
5. T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese, and A. B. Kahng, “Zero skew clock routing with minimum wirelength,” IEEE Trans. Circuits Syst., vol. 39, pp. 799–814, Nov. 1992.
6. F. L. Chao, “Timing skew of the equal-length serpentine routing,” in IEEE ASIC Symp., 1993, pp. 546–549.
7. A. Feller, H. R. Kaupp, and J. J. Digiacomo, “Crosstalk and reflections in high-speed digital systems,” in AFIPS Conf. Proc., 1965 Fall Joint Computer Conf., 1965, pp. 511–525.
8. K. J. Bathe and E. L. Wilson, Numerical Methods in Finite Element Analysis. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1976, pp. 452–460.
9. F. Romeo and M. Santomaro, “Time-domain simulation of n coupled transmission lines,” IEEE Trans. Microwave Theory Technol., vol. MTT-35, 35, pp. 131–136, Feb. 1987.
10. C. S. Chang, “Electrical design methodologies,” in Electronic Materials Handbook Vol. 1: Packaging. Materials Park, OH: ASM International, 1989, pp. 25–44.
11. W. T. Weeks, “Calculation of coefficients of capacitance of multiconductor ductor transmission lines in the presence of a dielectric interface,” IEEE Trans. Microwave Theory Technol., vol. MTT-18, p p. 35–43, Jan. 1970.
12. Microsim Corporation, Circuit Analysis Reference Manual, ver. 5.2, pp. 178–180, July 1992.