Performance Analysis of Decision-Feedback Equalization with Maximum-Likelihood Detector in High-Density Recording Channels

IEEE Transactions on Magnetics

Volumn 31, Issue 6, 1995, Pages 3063-3065

  Sawaguchi, Hideki ^a   Sakurai, Wataru ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; ELECTRIC FILTERS; ERROR DETECTION; FEEDBACK; INTERSYMBOL INTERFERENCE; PERFORMANCE; SIGNAL TO NOISE RATIO; WHITE NOISE;

DECISION-FEEDBACK EQUALIZATION; ERROR PROPAGATION; FEEDBACK-FILTER; FEEDBACK-LOOP; HIGH-DENSITY RECORDING CHANNELS; MAXIMUM-LIKELIHOOD DETECTOR; PERFORMANCE ANALYSIS; VITERIA ALGORITHMS;

MAGNETIC RECORDING;

EID: 0029408526     PISSN: 00189464     EISSN: 19410069     Source Type: Journal    
DOI: 10.1109/20.490270     Document Type: Article

References (9)

1. R.W Wood and D.A. Petersen, “Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel.”, IEEE Trans on Commun., vol. 34, No. 5, May 1986.
2. J.W.M. Bergmans, “Density Improvements in Digital Magnetic Recording by Decision Feedback Equalization.”, IEEE Trans on Magn. vol. 22, No. 5, May 1990.
3. H.K. Thapar and M. Patel, “A Class of Partial Response System for Increasing Storage Density in Magnetic Recording.”, IEEE Trans on Magn. vol. 23, No. 9, Sept. 1987.
4. J.W.M. Bergmans, et. al., “On the Use of Decision Feedback for Simplifying the Viterbi Detector.”, Philips J. Res., 42, No. 4, 1987.
5. J. Moon and L.R. Carley, “Performance Comparison of Detection Methods in Magnetic Recording.”, IEEE Trans on Magn. vol. 26, No. 6, Nov. 1990.
6. G.D. Forney, Jr., “Maximum-Likelihood Sequence Estimation of Digital Sequences in the Presence of Intersymbol Interference.”, IEEE Trans on IT, vol. 18, No. 3, May 1972.
7. D.G. Messerschmitt, “Design of Finite Impulse Response for the Viterbi Algorithm and Decision-Feedback Equalizer.”, Proc. ICC, 1974.
8. D.L. Duttweiler, J.E. Mazo, and D.G. Messerschmitt, “An Upper Bound on the Error Probability in Decision-Feedback Equalization.”, IEEE Trans on IT, vol. 20, No. 2, July 1974.
9. P.S. Bednarz, S.C. Lin, C.S. Modlin, and J.M. Cioffi, “Design, Performance, and Extensions of the RAM-DFE Architecture.”, IEEE Trans. on Magn. vol. 31, No. 2, March 1995.