An Analytical Model for Determining Carrier Transport Mechanism of Polysilicon Emitter Bipolar Transistors

IEEE Transactions on Electron Devices

Volumn 42, Issue 10, 1995, Pages 1789-1797

  Ma, Pingxi ^a   Zhang, Lichun ^a   Zhao, Baoying ^a   Wang, Yangyuan ^a  

^a PEKING UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; CURRENT DENSITY; DEPOSITION; DIFFUSION; ELECTRIC CONDUCTIVITY; ELECTRIC CURRENTS; ELECTRON TRANSPORT PROPERTIES; FERMI LEVEL; POLYCRYSTALLINE MATERIALS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS; TEMPERATURE;

CARRIER TRANSPORT MECHANISM; CURRENT GAIN; POLYSILICON EMITTER BIPOLAR TRANSISTOR; POLYSILICON SILICON INTERFACIAL OXIDE; SPECIFIC EMITTER INTERFACIAL RESISTIVITY; THERMIONIC EMISSION;

BIPOLAR TRANSISTORS;

EID: 0029393767     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.464417     Document Type: Letter

References (37)

1. M. Takagi, K. Nakayama, C. Tevada, and H. Kamioko, “Improvement of shallow base transistor technology by using a doping polysilicon diffusion source,” J. Jpn. Soc. Appl. Phys. (Suppl.), vol. 42, pp. 101-109, 1972.
2. J. Groul, A. Glast, and H. Murrmann, “High-performance transistors with arsenic-implanted polysil emitter,” IEEE J. Solid-State Circuits, vol. SC-11, pp. 491-495, 1976.
3. D. D. Tang, P. M. Solomon, T. H. Ning, R. D. Isaac, and R. E. Burger, “1.25 pm deep-groove-isolated self-aligned bipolar circuits,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 925-931, 1982.
4. S. Konaka, E. Yamamoto, K. Sakuma, Y. Amemiya, and T. Sakai, “A 20-ps Si bipolar IC using advanced super self-aligned process technology with collector ion implantation,” IEEE Trans. Electron Devices, vol. 36, pp. 1370-1375, 1989.
5. A. Nouailhat, G. Giroult, P. Delpech, and A. Gerodolle, “Development of an advanced CMOS compatible bipolar transistor for BiCMOS technology,” Electron. Lett., vol. 24, pp. 1581-1583, 1988.
6. M. P. Brassington, M. H. El-Diwary, R. R. Razouk, M. E. Thomas, and P. T. Tuntasood, “An advanced single-level polysilicon submicrometer BiCMOS technology,” IEEE Trans. Electron Devices, vol. 36, pp. 712-719, 1989.
7. T. Yamaguchi and T. H. Yuzuriha, “Process integration and device performance of a submicrometer BiCMOS with 16-GHz ft double polysilicon devices,” IEEE Trans. Electron Devices, vol. 36, pp. 890-896, 1989.
8. H. C. deGrooff and H. H. deGroot, “The SIS tunnel emitter: A theory for emitters with thin interface layers,” IEEE Trans. Electron Devices, vol. ED-26, no. 11, pp. 1771-1776, 1979.
9. T. H. Ning and P. D. Isaac, “Effect of emitter contact on current gain of silicon bipolar devices,” IEEE Trans. Electron Devices, vol. ED-27, pp. 2051-2055, 1980.
10. A. A. Eltoukhy and D. J. Roulston, “Minority-carrier injection into polysilicon emitters,” IEEE Trans. Electron Devices, vol. ED-29, p. 961, 1982.
11. C. C. Ng and E. S. Yang, “A thermionic-diffusion model of polysilicon emitter,” in IEDM Tech. Dig., pp. 28-31, 1986.
12. A. Neugroschel, M. Arienzo, Y. Komen, and R. D. Isaac, “Experimental study of the minority-carrier transport at the polysilicon-monosilicon interface,” IEEE Trans. Electron Devices, vol. ED-32, pp. 807-816, 1985.
13. A. A. Eltoukhy and D. J. Roulston, “The role of the interfacial layer in polysilicon emitter bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-29, pp. 1862-1869, Dec. 1982.
14. Z. Yu, B. Ricco, and R. W. Dutton, “A comprehensive analytical and numerical model of polysilicon emitter contacts in bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-31, pp. 773-784, 1984.
15. K. Suzuki, “Unified minority-carrier transport equation for polysilicon or heteromaterial emitter contact bipolar transistors,” IEEE Trans. Electron Devices, vol. 38, no. 8, pp. 1868-1877, 1991.
16. P. Ashbum, D. J. Roulston, and C. R. Selvakumar, “Comparison of experimental results on arsenic-and phosphorus-doped polysilicon emitter bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-34, pp. 1346-1353, 1987.
17. K. Sagara, T. Nakamura, Y.Tamaki, and T. Shiba, “The effect of thin interfacial oxides on the electrical characteristics of silicon bipolar devices,” IEEE Trans. Electron Devices, vol. ED-34. pp. 2286-2290, 1987.
18. P. A. Potyraj, D. L. Chen, M. K. Hatalis, and D. W. Greve, “Interfacial oxide, grain size, and hydrogen passivation effects on polysilicon emitter transistors,” IEEE Trans. Electron Devices, vol. 35, pp. 1334-1343, 1988.
19. P. Ashburn and B. Soerowirdjo, “Comparison of experimental and theoretical results on polysilicon emitter bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-31, pp. 853-860, 1984.
20. P. V. Halen and D. L. Pulfrey, “High-gain bipolar transistors with polysilicon tunnel junction emitter contacts,” IEEE Trans. Electron Devices, vol. ED-32, p. 1307, 1985.
21. I. R. C. Post, P. Ashburn, and G. R. Wolstenholme, “Polysilicon emitters for bipolar transistors: a review and re-evaluation of theory and experiment,” IEEE Trans. Electron Devices, vol. 39, pp. 1717-1730, 1992.
22. G. L. Patton, J. C. Bravman, and J. D. Plummer, “Physics, technology and modeling of polysilicon emitter contacts for VLSI bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-33, no. 11, pp. 1754-1768, 1986.
23. G. R. Wolstenholme, N. Jorgensen, P. Ashburn, and G. R. Booker, “An investigation of the thermal stability of the interfacial oxide in polycrystalline silicon emitter bipolar transistors by comparing device results with high-resolution electron microscopy observations,” J. Appl. Phys., vol. 61, pp. 225-233, 1987.
24. R. Stratton, “Volt-current characteristics for tunneling through insulating films,” J. Phys. Chem. Solids, vol. 33, pp. 1177, 1962.
25. H. C. Card and E. S. Yang, “Electronic process at grain boundaries in polycrystalline semiconductors under optical illumination,” IEEE Trans. Electron Devices, vol. ED-24, p. 397, 1977.
26. M. S. Tyahi and R. V. Overstraeten, “Minority carrier recombination in heavily-doped silicon,” +Solid-State Electron., vol. 26, pp. 577, 1983.
27. D. M. Kim, A. N. Khondker, S. S. Ahmed, and R. R. Shah, “Theory of conduction in polysilicon: Drift-diffusion approach in crystalline-amorphous-crystalline semiconductor system-Part 1: Small signal theory,” IEEE Trans. Electron Devices, vol. ED-31, p. 480, 1984.
28. L. A. Verhoef and W. C. Sinke, “Minority-carrier transport in nonuniformly doped silicon-An analytical approach,” IEEE Trans. Electron Devices, vol. 37, no. 1, pp. 210-221, 1990.
29. K. K. Ng and H. C. Card, “Asymmetry in the Si02 tunneling barriers to electrons and holes,” J. Appl. Phys., vol. 51, pp. 2153-2157, 1980.
30. S. E. Habib and J. G. Simmons, “Theory of switching in P-N-insulator(tunnel)-metal devices,” Solid-State Electron., vol. 23, p. 181, 1979.
31. E. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1969, p. 454.
32. T. M. Liu, Y. O. Kim, K. F. Lee, D. Y. Jeon, and A. Ourmazol, “The control of polysilicon/silicon interface processed by rapid thermal anneal,” IEEE BCTM, pp. 263-270, 1991.
33. J. M. Ziman, Principles of the Theory of Solids. New York: Cambridge, 1972, pp. 168-170.
34. C. Kittel, Introduction to Solid State Physics. New York: Wiley, 1971, p. 723.
35. S. S. Li and W. R. Thurber, “The dopant density and temperature dependence of electron mobility and resistivity in n-type silicon,” Solid-State Electron., no. 20, pp. 609-619, 1977.
36. S. S. Li, “The dopant density and temperature dependence of hole mobility and resistivity in boron doped silicon,” Solid-State Electron., no. 21, pp. 1109-1117, 1978.
37. J. C. S. Woo and J. D. Plummer, “Optimization of silicon bipolar transistor for high current gain at low temperatures,” IEEE Trans. Electron Devices, vol. 35, pp. 1311-1321, Aug. 1988.