VLSI Architecture for a Flexible Block Matching Processor

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 5, Issue 5, 1995, Pages 417-428

  Vos, Luc De ^a   Schobinger, Matthias ^a  

^a SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; EFFICIENCY; IMAGE PROCESSING; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; PARAMETER ESTIMATION; SYSTOLIC ARRAYS;

BLOCK MATCHING PROCESSOR; FLEXIBILITY; FLEXIBLE MEANDER LIKE DATA FLOW; HARDWARE OVERHEAD; QUADRATIC SYSTOLIC ARRAY ARCHITECTURE; SUB PIXEL ACCURACY; SUBSAMPLING WITH OFFSET; VARIABLE PIXEL RESOLUTION;

VLSI CIRCUITS;

EID: 0029386682     PISSN: 10518215     EISSN: 15582205     Source Type: Journal    
DOI: 10.1109/76.473554     Document Type: Article

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