Analysis and modelling of parasitic substrate coupling in CMOS circuits

IEE Proceedings: Circuits, Devices and Systems

Volumn 142, Issue 5, 1995, Pages 307-312

  Aragones, X ^a   Moll, F ^a   Roca, M ^a   Rubio, A ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR ANALYSIS; INTEGRATED CIRCUIT LAYOUT; RANDOM ACCESS STORAGE; SEMICONDUCTOR DEVICE MODELS; SPURIOUS SIGNAL NOISE; SUBSTRATES; TRANSISTORS; VLSI CIRCUITS;

PARASITIC SUBSTRATE COUPLING;

CMOS INTEGRATED CIRCUITS;

EID: 0029386556     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:19952164     Document Type: Article

References (12)