Sub-1/4-µm Dual-Gate CMOS Technology Using In-Situ Doped Polysilicon for nMOS and pMOS Gates

IEEE Transactions on Electron Devices

Volumn 42, Issue 9, 1995, Pages 1583-1590

  Okazaki, Yukio ^a   Kobayashi, Toshio ^a   Inokawa, Hiroshi ^a   Nakayama, Satoshi ^a   Miyake, Masayasu ^a   Morimoto, Takashi ^a   Yamamoto, Yousuke ^b  

^a NTT CORPORATION   (Japan)

^b TAMAGAWA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BORON; CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; FREQUENCY DIVIDING CIRCUITS; IN SITU PROCESSING; MOS DEVICES; MULTILAYERS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING;

BORON PENETRATION; DOPANTS; HIGH-TEMPERATURE DIFFUSION; POLYSILICON; THIN GATE OXIDE; TRANSISTOR MEASUREMENT;

GATES (TRANSISTOR);

EID: 0029379256     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.405271     Document Type: Article

References (19)

1. G. J. Hu and R. H. Bruce, “Design tradeoffs between surface and buried-channel FET's,” IEEE Trans. Electron Devices, vol. 32, p. 584, 1985.
2. K. Tanaka and M. Fukuma, “Design methodology for deep submicron CMOS,” in IEDM Tech. Dig., 1987, p. 87.
3. J. Y.-C. Sun, C. Wong, Y. Taur, and C.-H. Hsu, “Study of boron penetration through thin oxide with p+ polysilicon gate,” in 1985 Symp. VLSI Technol. Dig., p. 17.
4. F. K. Baker et al., “The influence of fluorine on threshold voltage instability in p+ polysilicon gates p-channel MOSFETs,” in IEDM Tech. Dig., 1989, p. 443.
5. K. Uwasawa et al., “Scaling limitation of gate oxide in p+ polysilicon gate MOS structures for sub-quarter micron CMOS devices,” in IEDM Tech. Dig., 1993, p. 895.
6. C. Y. Wong et al., “Doping of n+ and p+ polysilicon in a dual-gate CMOS process,” in IEDM Tech. Dig., 1988, p. 238.
7. S. Nakayama, “A p+ poly-Si gate with nitrogen-doped poly-Si layer for deep submicron pMOSFETs,” in 1991 ECS Spring Meeting, Proc. Int. Symp. ULSI Science and Technol., p. 9.
8. Y. Okazaki, S. Nakayama, M. Miyake, and T. Kobayashi, “Characteristics of sub-1/4-µm gate surface channel PMOSFETs using a multilayer gate structure of boron-doped poly-Si on thin nitrogen-doped poly-Si,” IEEE Trans. Electron Devices, vol. 41, p. 2369, 1994.
9. Y. Okazaki et al., “Sub-1/4 µm dual gate CMOS technology using in situ doped polysilicon for n and pMOS gates,” in 1993 Symp. VLSI Technol. Dig., p. 95.
10. Y. Okazaki et al., “Characteristics of a new isolated p-well structure using thin epitaxy over the buried layer and trench isolation,” IEEE Trans. Electron Devices, vol. 39, p. 2758, 1992.
11. H. Inokawa et al., “Ultranarrow trench-isolated 0.2 µm CMOS and its application to ultralow-power frequency divider,” in IEDM Tech. Dig., 1993, p. 887.
12. M. Miyake, T. Kobayashi, and Y. Okazaki, “Subquarter-micrometer gate-length p-channel and n-channel MOSFET's with extremely shallow source-drain junctions,” IEEE Trans. Electron Devices, vol. 36, p. 392, 1989.
13. T. Ohno, Y. Kado, M. Harada, and T. Tsuchiya, “A high-performance quarter-micron CMOS/SIMOX technology,” in 1993 Symp. VLSI Technol. Dig., p. 25.
14. K. Deguchi et al., “Application of X-ray lithography with a single-layer resist process to subquartermicron large scale integrated circuit fabrication,” J. Vac. Sci. Technol. B, vol. 10, p. 3145, 1992.
15. S. Nakayama, H. Yonezawa, and J. Murota, “Deposition of phosphorous doped silicon films by thermal decomposition of disilane,” Jpn. J. Appl. Physics., vol. 23, p. L493, 1984.
16. S. Nakayama, I. Kawashima, and J. Murota, “Boron doping effects on silicon film deposition in the Si2H6-He gas system,” J Electrochem. Soc., vol. 133, no. 8, p. 1721, 1986.
17. E. Kinsborn, M. Sternheim, and R. Knoell, “Crystallization of amorphous silicon films during low pressure chemical vapor deposition,” Appl. Phys. Lett., vol. 42, no. 9, p. 835, 1983.
18. T. Morimoto, “Influence of reaction products on Si gate etching with a photoresist mask in HBr/O2 and Cl2/O2 electron cyclotron resonance plasma,” Jpn. J. Appl. Physics., vol. 32, p. 1253, 1993.
19. M. Takahashi et al., “Anomalous resistance in 0.1 µm-region Ti-silicided poly Si gate,” in Extended Abstract 1993 Int. Conf. Solid State Devices and Materials, p. 458.