CMOS Analog Divider and Four-Quadrant Multiplier Using Pool Circuits

IEEE Journal of Solid-State Circuits

Volumn 30, Issue 9, 1995, Pages 1025-1029

  Liu, Shen Iuan ^a   Chang, Cheng Chieh ^b  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; DIVIDING CIRCUITS (ARITHMETIC); ELECTRIC CURRENTS; MOSFET DEVICES; MULTIPLYING CIRCUITS; NUMERICAL ANALYSIS; SIGNAL PROCESSING;

ANALOG SIGNAL PROCESSING; CMOS ANALOG DIVIDER; CMOS DIFFERENTIAL AMPLIFIER; FOUR QUADRANT MULTIPLIER; POOL CIRCUITS; THRESHOLD VOLTAGE;

DIGITAL CIRCUITS;

EID: 0029373159     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.406403     Document Type: Article

References (16)

1. C. Mead and M. Ismail, Analog VLSI Implementation of Neural Systems. Norwell, MA: Kluwer, 1989.
2. D. H. Sheingold, Ed., Nonlinear Circuit Handbook. Norwood, MA: Analog Devices, 1974.
3. T. Yamakawa, “High-speed fuzzy controller hardware system: The mega-FIPS machine,” Inform. Sci., vol. 45, pp. 113–128, 1988.
4. E. Sanchez-Sinencio, J. Ramirez-Angulo, B. Linares-Barranco, and A. Rodriguez-Vazquez, “Operational transconductance amplifier-based nonlinear function synthesis,” IEEE J. Solid-State Circuits, vol. 24, pp. 1576–1586, Dec. 1989.
5. D. Ghosh and D. Patranabis, “A simple analog divider having independent control of sensitivity and design condition,” IEEE Trans. Instrum. Meas., vol. 39, pp. 522–526, June 1990.
6. Th. L. Laoppoulos and C. A. Karybakas, “A simple analog division scheme,” IEEE Trans. Instrum. Meas., vol. 40, pp. 779–782, Aug. 1991.
7. N. I. Khachab and M. Ismail, “A nonlinear CMOS analog cell for VLSI signal and information processing,” IEEE J. of Solid-State Circuits, vol. 26, pp. 1689–1698, Nov. 1991.
8. P. Aronhime, M. Desai, and J. Stephens, “Quotient circuits employing VVR,” IEEE Trans. Instrum. Meas., vol. 41, pp. 679–684, Oct. 1992.
9. S. I. Liu, D. S. Wu, H. W. Tsao, J. Wu, and J. H. Tsay, “Nonlinear circuit applications with current conveyors,” IEE Proc.-G, vol. 140, pp. 1–6, Feb. 1993.
10. R. R. Torrance, T. R. Viswanathan, and J. V. Hanson, “CMOS voltage to current transducers,” IEEE Trans. Circuits Syst., vol. CAS-32, pp. 1097–1104, Nov. 1985.
11. S. W. Tsay and R. Newcomb, “A neuro-type pool arithmetic unit,” in Proc. IEEE ISCAS'91 (Singapore), 1991, pp. 2518–2521.
12. H. J. Song and C. K. Kim, “An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers,” IEEE J. Solid-State Circuits, vol. 25, pp. 841–847, June 1990.
13. S. I. Liu and Y. S. Hwang, “CMOS four-quadrant multiplier using bias-offset crosscoupled pairs,” Electron. Lett., vol. 20, pp. 1737–1738, Sept. 1993.
14. S. P. Singh, J. V. Hanson, and J. Vlach, “A new floating resistor for CMOS technology,” IEEE Trans. Circuits Syst., vol. 36, pp. 1217–1220, Sept. 1989.
15. Z. Wang, “Automatic VT extractors based on an n x n2 MOS transistor array and their application,” IEEE J. Solid-State Circuits, vol. 27, pp. 1277–1285, Sept. 1992.
16. S. Wong and C. A. Salama, “Impact of scaling on MOS analog performance,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 106–114, Feb. 1983.