Effects of Measurement Frequency and Temperature Anneal on Differential Gate Capacitance Spectra Observed in Hot Carrier Stressed MOSFET's

IEEE Transactions on Electron Devices

Volumn 42, Issue 8, 1995, Pages 1528-1535

  Ling, C H ^a   Ang, D S ^a   Tan, S E ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITANCE MEASUREMENT; ELECTRIC FREQUENCY MEASUREMENT; ENERGY GAP; GATES (TRANSISTOR); HOT CARRIERS; INTERFACES (MATERIALS); SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR JUNCTIONS; SUBSTRATES; TEMPERATURE MEASUREMENT;

ACCEPTOR INTERFACE TRAPS; DIFFERENTIAL GATE CAPACITANCE SPECTRA; DRAIN JUNCTION; GATE OXIDE; TEMPERATURE ANNEAL;

MOSFET DEVICES;

EID: 0029359211     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.398669     Document Type: Article

References (23)

1. G. Groeseneken, H. E. Maes, N. Beltran, and R. F. de Keersmaecker, “A reliable approach to charge-pumping measurements in MOS transistors,” IEEE Trans. Electron Devices, vol. ED-31, pp. 42-53, 1984.
2. C. H. Ling, Y. T. Yeow, and L. K. Ah, “Characterization of charge trapping in submicrometer NMOSFET's by gate capacitance measurements,” IEEE Electron Device Lett, vol. 12, pp. 587-589, 1992.
3. C. H. Ling, “Electron trapping the interface state generation in PMOS-FET's: results from gate capacitance,” Jpn. J. Appl. Phys., vol. 32, pp. L1371-L1373, 1993.
4. N. M. Johnson, D. K. Biegelsen, M. D. Moyer, and S. T. Chang, “Characteristic electronic defects at the Si-SiO2 interface,” Appl. Phys. Lett., vol. 43, pp. 563-565, 1983.
5. E. H. Poindexter, “MOS interface states: overview and physicochemical perspective,” Semicond. Sci. Technol., vol. 4, pp. 961-969, 1989.
6. E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor Physics and Technology). Singapore: John Wiley, 1991.
7. E. Takeda, Y. Nakagome, H. Kume, N. Suzuki, and S. Asai, “Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's,” IEEE Trans. Electron Devices., vol. ED-30, pp. 675-680, 1983.
8. K. K. Ng and G. W. Taylor, “Effects of hot-carrier trapping in n- and p-channel MOSFET's,” IEEE Trans. Electron Devices., vol. ED-30, pp. 871-876, 1983.
9. T. Tsuchiya and J. Frey, “Relationship between hot-electrons/holes and degradation of p- and n-channel MOSFET's,” IEEE Electron Device Lett., vol. EDL-6, pp. 8-10, 1985.
10. Q. Wang, M. Brox, W. H. Krautschneider, and W. Weber, “Explanation and model for the logarithmic time dependence of p-MOSFET degradation,” IEEE Electron Device Lett., vol. 12, pp. 218-220, 1991.
11. N. S. Saks and M. G. Ancona, “Spatial uniformity of interface trap distribution in MOSFET's,” IEEE Trans. Electron Devices, vol. 37, pp. 1057-1063, 1990.
12. K. C. K. Weng and P. Yang, “A direct measurement technique for small geometry MOS transistor capacitances,” IEEE Electron Device Lett, vol. EDL-6, pp. 40-42, 1985.
13. Y. T. Yeow, “Measurement and numerical modeling of short-channel MOSFET gate capacitances,” IEEE Trans. Electron Devices, vol. ED-34, pp. 2510-2520, 1987.
14. K. Yamabe and Y. Miura, “Discharge of trapped electrons from MOS structures,” J. Appl. Phys., vol. 51, pp. 6258-6264, 1980.
15. A. J. Lelis, T. R. Oldham, H. E. Boesch, Jr., and F. B. McLean, “The nature of the trapped hole annealing process,” IEEE Trans. Nucl. Sci., vol. 36, pp. 1808-1815, 1989.
16. C. H. Ling, B. P. Seah, G. S. Samudra, and C. H. Gan, “Measurement and simulation of hot carrier degradation in PMOSFET by gate capacitance,” IEEE Trans. Electron Devices, vol. 42, pp. 928-934, May 1995.
17. N. Haneji, L. Vishnubhotla, and T. P. Ma, “Possible observation of Pbo and Pb1 centres at irradiated (100) Si/Si02 interface from electrical measurements,” Appl. Phys. Lett., vol. 59, pp. 3416-3418, 1991.
18. G. J. Gerardi, E. H. Poindexter, P. J. Caplan, and N. M. Johnson, “Interface traps and Pb, centres in oxidized (100) silicon wafers,” Appl. Phys. Lett., vol. 49, pp. 348-350, 1986.
19. Y. Nishioka, E. F. da Silva, and T. P. Ma, “Equivalence between interface traps in Si/Si02 generated by radiation damage and hot-electron injection,” Appl. Phys. Lett., vol. 52, pp. 720-722, 1988.
20. T. P. Ma, “Interface trap transformation in radiation or hot-electron damaged MOS structures,” Semicond. Sci. Technol, vol. 4, pp. 1061-1079, 1989.
21. T. P. Ma and P. V. Dressendorfer, Ionizing Radiation Effects in MOS Devices and Circuits. New York: Wiley, 1989.
22. B. J. Fishbein, J. T. Watt, and J. D. Plummer, ‘Time resolved annealing of interface traps in polysilicon gate metai-oxide-silicon capacitors,” J. Electrochem. Soc., vol. 134, pp. 674-681, 1987.
23. C. T. San, “Models and experiments on degradation of oxidized silicon,” Solid-State Electron., vol. 33, pp. 147-167, 1990.