RNS-Based Enhancements for Direct Digital Frequency Synthesis

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 42, Issue 8, 1995, Pages 516-524

  Chren, William A ^a  

^a GRAND VALLEY STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK SYNTHESIS; MICROPROCESSOR CHIPS; TABLE LOOKUP;

DIRECT DIGITAL FREQUENCY SYNTHESIS; FREQUENCY AGILE DIRECT SYNTHESIZER; LATENCY; PHASE ACCUMULATORS; REDUCED AREA DIRECT SYNTHESIZER; RESIDUE NUMBER SYSTEM;

FREQUENCY SYNTHESIZERS;

EID: 0029358443     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.404073     Document Type: Article

References (17)

1. V. Manassewitsch, Frequency Synthesizers, Theory and Design. New York: Wiley, 1979, 2nd ed., p. 54.
2. A. Edwin, “Direct digital synthesis applications,” Microwave J., vol. 33, no. 1,pp. 149-151, Jan. 1990.
3. J. Tierney, C. M. Rader, and B. Gold, “A digital frequency synthesizer,” IEEE Trans. Audio and Electroacoust., vol. AU-19, no. 1, pp. 48-56, Mar. 1971.
4. P. H. Saul and S. J. Mudd, “A direct digital synthesizer with output capability,” IEEE J. Solid State Circuits, vol. 23, no. 3, pp. 819-821, June 1988.
5. P. H. Saul and D. G. Taylor, “A high-speed direct frequency synthesizer,” IEEE J. Solid State Circuits, vol. 25, no. 1, pp. 215-219, Feb. 1990.
6. H. T. Nicholas, III and H. Samueli, “An analysis of the output spectrum of direct digital frequency synthesizers in the presence of phase-accumulator truncation,” in Proc. 41st Annu. Freq. Contr. Symp., May 1987, p. 496.
7. M. Thompson, “Low-latency, high-speed using progression-of-states technique,” IEEE J. Solid State Circuits, vol. 27, no. 1, pp. 113-117, Jan. 1992.
8. B. Giebel, J. Lutz, and P. L. O’Leary, “Digitally controlled oscillator,” IEEE J. Solid State Circuits, vol. 24, no. 6, pp. 640-645, June 1989.
9. F. Lu, H. Samueli, J. Yuan, and C. Svensson, “A 700-MHz 24-bit pipelined accumulator in 1.2µ CMOS for applications as a numerically controlled oscillator,” in IEEE 1991 Custom Integrat. Circuits Conf. Proc., p. 25.3.2.
10. W. A. Chren, Jr., “A new residue number system division algorithm,” Computers and Mathematics With Applications, vol. 19, no. 7, pp. 13-29.
11. N. S. Szabo and R. I. Tanaka, Residue Arithmetic and Its Applications to Computer Technology. New York: McGraw-Hill, 1967, pp. 147-151.
12. W. K. Jenkins, “Techniques for residue-to-analog conversion for residue-encoded digital filters,” IEEE Trans. Circuits Syst., vol. CAS-25, pp. 555-562, July 1978.
13. M. A. Soderstrand, C. Vernia, and J. H. Chang, “An improved residue number system digital-to-analog converter,” IEEE Trans. Circuits Syst., vol. CAS-30, pp. 903-907, Dec. 1983.
14. N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, A Systems Perspective. Reading, MA: Addison Wesley, 1993, 2nd ed., pp. 516-517.
15. N. R. Shanbhag and R. E. Siferd, “A single-chip pipelined 2-D FIR filter using residue arithmetic,” IEEE J. Solid-State Circuits, vol. 26, pp. 796-805, May 1991.
16. F. Lu, H. Samueli, J. Yuan, and C. Svensson, “A 700-MHz 24-bit pipelined accumulator in 1.2µ CMOS for application as a numerically controlled oscillator,” IEEE J. Solid State Circuits, vol. 28, p. 879, Aug. 1993.
17. D. K. Banerji and J. A. Brzozowski, “On translation algorithms in residue number systems,” IEEE Trans. Comput., vol. C-21, pp. 1281-1285, Dec. 1972.