An Integrated CMOS 0.15 ns Digital Timing Generator for TDC's and Clock Distribution Systems

IEEE Transactions on Nuclear Science

Volumn 42, Issue 4, 1995, Pages 753-757

  Christiansen, J ^a  

^a CERN   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BUFFER STORAGE; CAPACITORS; CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; ELECTRIC CLOCKS; ELECTRIC CURRENTS; PARTICLE DETECTORS; TIMING CIRCUITS;

ASYNCHRONOUS PIPELINE BUFFER; CLOCK DISTRIBUTION SYSTEMS; CURRENT INTEGRATOR; DELAY LOCKED LOOPS; TIME TO DIGITAL CONVERSION; TIMING GENERATOR;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029357418     PISSN: 00189499     EISSN: 15581578     Source Type: Journal    
DOI: 10.1109/23.467797     Document Type: Article

References (13)

1. J. Christiansen et al., An Integrated 16-channel CMOS Time to Digital Converter, Nuclear Science Sym. 1993, pp 625 - 629.
2. Y. Arai et al., A CMOS four channel x 1K Time Memory LSI with 1ns/b Resolution, IEEE J. Solid-State Circuits, Vol. 27, No. 3, March 1992
3. S. Kleinfelder et al., The MTD132 - A new sub-nanosecond multi-hit CMOS Time to Digital Converter, IEEE Trans. on Nuclear Science, Vol. 38, No. 2, April 1991.
4. T. Rahkonen et al., The use of stabilized CMOS delay lines for the digitization of short time intervals. J. Solid-State Circuits, Vol. 28, No. 8, pp 887 - 894, August 1993.
5. M. Pelgrom et al., Matching properties of MOS transistors. IEEE J. Solid-State Circuits, Vol. 24, No. 5, pp 1433–1439, Oct. 1989.
6. T. Knotts et al., A 500 MHz Time Digitizer IC with 15.625ps Resolution, ISSCC 95, pp 58 - 59.
7. C. Neyer, R. Schulze, Developments of a fast time to analog converter, presented at ALICE TOF electronics meeting at CERN june 23 1994.
8. M. Johnson, E. Hudson, A Variable delay line for CPU co-processor synchronization, IEEE J. Solid-State Circuits, Vol. 23, No. 23, pp 1218 - 1223, Oct. 1988.
9. I. Sutherland, Micro-pipelines, Communications of the ACM, Vol. 32, No. 6, June 1989.
10. J. Christiansen et al., A Micro-Pipelined Zero Suppression, Trigger matching and Recalibration Integrated Circuit, Nuclear Science Sym. 1992, pp 477 - 479.
11. B. Taylor, Optical Timing, Trigger and Control Distribution for LHC Detectors, Nuclear Science Sym. 1993, pp. 777 - 781.
12. D. Wolaver, Phase Locked Loop Circuit Design, Prentice Hall.
13. Letter of intent for the ALICE experiment, CERN/LHCC/93-16.