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Volumn 10, Issue 3, 1995, Pages 225-236

VLSI architecture for fast 2D discrete orthonormal wavelet transform

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; DIGITAL FILTERS; IMAGE ANALYSIS; ONLINE SYSTEMS; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; REAL TIME SYSTEMS; SIGNAL PROCESSING; SIGNAL THEORY; WAVELET TRANSFORMS;

EID: 0029349822     PISSN: 09225773     EISSN: 1573109X     Source Type: Journal    
DOI: 10.1007/BF02120030     Document Type: Article
Times cited : (28)

References (14)
  • 9
    • 84936524273 scopus 로고    scopus 로고
    • K.K. Parhi and T. Nishitani, “Folded VLSI Architectures for Discrete Wavelet Transforms,”Proc. IEEE ISCAS, pp. 1734–1737, 1993.
  • 12
    • 84936524276 scopus 로고    scopus 로고
    • H.Y.H. Chuang and L. Chen, “ Scalable VLSI parallel pipelined architecture for discrete wavelet transform,”Proc. SPIE: Machine Vision Applications, Architectures, and Systems Integration II, Boston, MA, pp. 66–73, Sept. 1993.
  • 13
    • 84936524275 scopus 로고    scopus 로고
    • H.T. Kung, “Why Systolic Architectures?”IEEE Computer Magazine, pp. 37–46, January 1982.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.