A Simple Method to Extract the Asymmetry in Parasitic Source and Drain Resistances from Measurements on a MOS Transistor

IEEE Transactions on Electron Devices

Volumn 42, Issue 7, 1995, Pages 1388-1390

  Kolk, J ^b   King, M I H ^b  

^a SIMON FRASER UNIVERSITY   (Canada)

^b NORTEL NETWORKS   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC RESISTANCE MEASUREMENT; HOT CARRIERS; INTEGRATED CIRCUIT LAYOUT; SATURATION (MATERIALS COMPOSITION); STRESS ANALYSIS;

DRAIN RESISTANCE; GATE TERMINALS; HOT CARRIER STRESSING; PARASITIC SOURCE;

MOSFET DEVICES;

EID: 0029346632     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.391229     Document Type: Article

References (6)

1. P. I. Suciu and R. L. Johnston, “Experimental derivation of the source and drain resistance of MOS transistors,” IEEE Trans. Electron Devices, vol. ED-27, pp. 1846–1848, 1980.
2. K. K. Ng and J. R. Brews, “Measuring the effective channel length of MOSFET's,” IEEE Circuits and Devices Magazine, vol. 6, pp. 33–38, Nov. 1990.
3. Z. P. Zuo, M. J. Deen, and J. Wang, “A new method for extracting short-channel length or narrow-channel width MOSFET linear parameters,” in Proc. Canadian Conf. Electrical and Computer Eng., Sept. 17–20, 1989, pp. 1038–1041.
4. S. T. Hsu, “A simple method to determine series resistance and k factor of an MOS field effect transistor,” RCA Review, vol. 44, pp. 424–429, 1983.
5. B. Ricco, L. Selmi, and E. Sangiorgi, “A novel method to determine the source and drain resistances of individual MOSFET's,” IEDM Technical Digest, pp. 122–125, 1988.
6. S. Y. Chou and D. A. Antoniadis, “Relationship between measured and intrinsic transconductances of FET's,” IEEE Trans. Electron Devices, vol. ED-34, pp. 448–450, 1987.