Highly Suppressed Boron Penetration in NO-Nitrided SiO2 for p+ -Polysilicon Gated MOS Device Applications

IEEE Electron Device Letters

Volumn 16, Issue 7, 1995, Pages 319-321

  Han, L K ^a   Wristers, D ^a   Yan, J ^a   Bhat, M ^a   Kwong, D L ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BORON; CAPACITANCE; ELECTRIC BREAKDOWN; ELECTRIC CHARGE; ELECTRIC RESISTANCE; GATES (TRANSISTOR); NITRIDING; NITROGEN OXIDES; SEMICONDUCTING SILICON; SILICA;

BORON PENETRATION EFFECTS; DIFFUSION BARRIER PROPERTIES; INTERFACE STATE DENSITY; POLYSILICON; SURFACE CHANNEL PMOS TECHNOLOGY;

MOS DEVICES;

EID: 0029345915     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.388720     Document Type: Article

References (16)

1. G. Hu and R. H. Bruce, “Design tradeoffs between surface and buried-channel FET's,” IEEE Trans. Electron Devices, vol. ED-32, p. 584, 1985.
2. S. J. Hillenius and W. T. Lynch, “Gate material work function consideration for 0.5 micron CMOS,” IEDM Tech. Dig., p. 147. 198 5.
3. J. R. Pfiester, F. K. Baker, T. C. Mele, H.-H. Tseng, P. J. Tobin, J. D. Hayden, J. W. Miller, C. D. Gunderson, and L. C. Parrillo, “The effects of boron penetration on p + polysilicon gated PMOS devices,” IEEE Trans. Electron Devices. vol. 37. p. 1842. 1990.
4. J. Y.-C. Sun, C. Wong, Y. Taur and C.-H. Hsu, “Study of boron penetration through thin oxide with p + -polysilicon gate,” in Tech. Dig. Symp. VLSI Tech., 1989. p 17.
5. H. Hayashida, Y. Toyoshima, Y. Suizu, K. Mitsuhashi, H. Iwai, and K. Maeguchi, “Dopant redistribution in dual gate W -polycide CMOS and its improvement by RTA.” in Tech. Die. Symp. VLSI Tech., 1989. n. 29.
6. T. Morimoto, H. S. Momose, Y. Ozawa, K. Yamabe and H. Iwai, “Effects of boron penetration and resultant limitations in ultra thinpure-oxide and nitrided-oxide gate-films,” IEDM Tech. Dig., p. 429, 1990.
7. A. B. Joshi, J. Ahn and D. L. Kwong, “Oxynitride gate dielectrics for p + -polysilicon gate MOS devices,” IEEE Electron Device Lett., vol. 14. p. 560. 1993.
8. G. Q. Lo and D. L. Kwong, ‘’The use of ultrathin reoxidized nitrided gate oxide for suppression of boron penetration in BF + 2 -implanted polysilicon gated p-MOSFET‘s,” IEEE Electron Device Lett., vol. 12, p, 175. 1991.
9. H. Fang. K. S. Krisch. B. J. Gross. C. G. Sodini, J. Chung, and D. A. Antoniadis, “Low-temperature furnace grown reoxidized nitrided oxide gate dielectrics as a barrier to boron penetration,” IEEE Electron Device Lett. vol. 13. p. 217. 1992.
10. Z. J. Ma, J. C.Chen, Z. H. L i u, J. T. Krick, Y. C. Cheng, C. Hu, and P. K. Ko, “Suppression of boron penetration in p + -polysilicon gate p-MOSFET‘s using low temperature gate-oxide N 2 O anneal,” IEEE Electron Device Lett., vol. 15. p. 109. 1994.
11. T. Hori, H. Iwasaki. and K. Tsuji. “Charge trapping properties of ultrathin nitrided oxides prepared by rapid thermal annealing,” IEEE Trans. Electron Devices. vol. 35. p. 904. 1988.
12. M. Bhat, D. Wristers, J. Yan, L. K. Han, J. Fulford, and D. L Kwong, “ Performance and hot-carrier reliability of n- and p-MOSFETs with rapid thermally NO-nitrided SiO2 gate dielectrics,” IEDM Tech. Dig., p. 329, 1994.
13. C. Y. Wong, J. Y.-C. Sun, Y. Taur, C. S. Oh, R. Angelucci, and B. Davari, “Doping of n + and p + -polysilicon in a dual-gate CMOS process,” IEDM Tech. Dig., p. 238, 1988.
14. S.-W. Lee, C. Liang, C.-S. Pan, W. Lin, and J. B. Mark. “A study on the physical mechanism in the recovery of gate capacitance to Cox in implanted polysilicon MOS structures,” IEEE Electron Device Lett., vol. 13. p. 2. 1992.
15. J. S. Cable, R. A. Mann and J. C. S. Woo, “Impurity barrier properties of reoxidized nitrided oxide films for use with p + -doped polysilicon gates,” IEEE Electron Device Lett., vol. 12, p. 128, 1991.
16. G. Q. Lo, D. L. Kwong and S. Lee, “Anomalous capacitance-voltage characteristics of BFz-implanted and rapid thermal annealed p+- polycrystalline silicon gate metal-oxide-semiconductor structures,” Appl. Phys. Lett., vol. 57, p. 2573, 1990.