A Study of Hot Carrier Degradation in NMOSFET's by Gate Capacitance and Charge Pumping Current

IEEE Transactions on Electron Devices

Volumn 42, Issue 7, 1995, Pages 1321-1328

  Ling, C H ^a   Tan, S E ^a   Ang, D S ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CAPACITANCE; CHARGE CARRIERS; DEGRADATION; ELECTRIC CURRENTS; ELECTRON TRANSPORT PROPERTIES; GATES (TRANSISTOR); HOT CARRIERS; INTERFACES (MATERIALS); SEMICONDUCTOR DEVICE STRUCTURES; STRESS ANALYSIS; THERMAL EFFECTS;

CHARGE PUMPING CURRENT; GATE CAPACITANCE; GATE STRESS VOLTAGE; HOT CARRIER DEGRADATION; INTERFACE TRAPS; THRESHOLD VOLTAGE;

MOSFET DEVICES;

EID: 0029345912     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.391215     Document Type: Article

References (23)

1. H. Gesch, J. P. Leburton and G. E. Dorda, “Generation of interface states by hot-hole injection in MOSFET's,” IEEE Trans. Electron Devices, vol. ED-29, pp. 913–918, 1982.
2. K. K. Ng and G. W. Taylor, “Effects of hot-carrier trapping in n- and p-channel MOSFET's,” IEEE Trans. Electron Devices, vol. ED-30, pp. 871–876, 1983.
3. E. Takeda, A. Shimizu and T. Hagiwara, “Role of hot-hole injection in hot-carrier effect and the small degraded channel region in MOSFET's,” IEEE Electron Device Lett., vol. EDL-4, pp. 329–331, 1983.
4. E. Takeda, Y. Nakagome, H. Kume, N. Suzuki and S. Asai, “Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's,” IEEE Trans. Electron Devices, vol. ED-30, pp. 675–680, 1983.
5. K. R. Hofmann, C. Werner, W. Weber and G. Dorda, “Hot-electron and hole-emission effects in short n-channel MOSFET's,” IEEE Trans. Electron Devices, vol. ED-32, pp. 691–699, 1985.
6. S. K. Lai, “Interface trap generation in silicon dioxide when electrons are captured by trapped holes,” J. Appl. Phys., vol. 54, pp. 2540–2546, 1983
7. Y. T. Yeow, C. H. Ling and L. K. Ah, “Observation of MOSFET degradation due to electrical stressing through gate-to-source and gate-to-drain capacitance measurement,” IEEE Electron Device Lett., vol. 12, pp. 366–368, 1991.
8. C. H. Ling, Y. T. Yeow and L. K. Ah, “Characterization of charge trapping in submicrometer NMOSFET's by gate capacitance measurements,” IEEE Electron Device Lett., vol. 13, pp. 587–589, 1992.
9. P. Heremans, J. Witters, G. Groeseneken and H. E. Maes, “Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation,” IEEE Trans. Electron Devices, vol. 36, pp. 1318–1335, 1989.
10. E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology. New York: John Wiley, 1991.
11. C. H. Ling, “Trap generation at Si/SiO2 interface in submicrometer metal-oxide-semiconductor transistors by 4.9 eV ultraviolet irradiation,” J. Appl. Phys., vol. 76, pp. 581–583, 1994.
12. G. J. Gerardi, E. H. Poindexter, P. J. Caplan and N. M. Johnson, “Interface traps and Pb centers in oxidized (100) silicon wafers,” Appl. Phys. Lett., vol. 49, pp. 348–350, 1986.
13. C. H. Ling, “Electron trapping and interface state generation in PMOSFET's: results from gate capacitance,” Japan J. Appl. Phys., vol. 32, L1371–L1373, 1993
14. E. H. Poindexter, P. J. Caplan, J. J. Finnegan, N. M. Johnson, D. K. Biegelsen and M. D. Moyer, “Surface-potential dependence of EPR centers at the Si/SiO2 interface,” The Physics of MOS Insulators, G. Lucovsky, S. T. Pantelides and F. L. Galeener, Eds. New York: Pergamon, 1980, pp. 326.
15. R. Woltjer and G. M. Paulzen, “A new monitor to predict hot-carrier damage of PMOS transistors,” IEDM Tech. Dig., pp. 561–564, 1990
16. Q. Wang, M. Brox, W. H. Krautschneider, and W. Weber, “Explanation and model for logarithmic time dependence of p-MOSFET degradation,” IEEE Electron Device Lett., vol. 12, pp. 218–220, 1991.
17. S. S. Nelson and M. G. Ancona, “Spatial uniformity of interface trap distribution in MOSFET's,” IEEE Trans. Electron Devices, vol. 37, pp. 1057–1063, 1990.
18. M. L. Reed and J. D. Plummer, Si-SiO2 interface trap production by low-temperature thermal processing,” Appl. Phys. Lett., vol. 15, pp. 514–516, 1987.
19. N. M. Johnson, D. K. Biegelsen, M. D. Moyer, S. T. Chang, E. H. Poindexter and P. J. Caplan, “Characteristic electronic defects at the Si-SiO2 interface,” Appl. Phys. Lett., vol. 43, pp. 563–565, 1983.
20. K. L. Brower, “Passivation of paramagnetic Si-SiO2 interface states with molecular hydrogen,” Appl. Phys. Lett., vol. 53, pp. 508–510, 1988.
21. M. L. Reed and J. D. Plummer, “Chemistry of Si-SiO2 interface trap annealing,” J. Appl. Phys., vol. 63, pp. 5776–5793, 1988.
22. B. J. Fishbein, J. T. Watt and J. D. Plummer, “Time resolved annealing of interface traps in polysilicon gate metal-oxide-silicon capacitors,” J. Electrochem. Soc., vol. 134, pp. 674–681, 1987.
23. R. Bellens, E. de Schrijver, G. van den bosch, G. Groeseneken, P. Heremans and H. E. Maes, “On the hot-carrier-induced post-stress interface trap generation in n-channel MOS transistors,” IEEE Trans. Electron Devices, vol. 41, pp. 413–419, 1994.