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Journal of VLSI Signal Processing

Volumn 10, Issue 2, 1995, Pages 153-168

Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers

(4) Caire, G a Ventura Traveset, J b Hollreiser, M b Biglieri, E a

a POLITECNICO DI TORINO (Italy)

b EUROPEAN SPACE AGENCY (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK CODES; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; DECODING; DIGITAL SIGNAL PROCESSING; MODULATION; PIPELINE PROCESSING SYSTEMS; TRELLIS CODES; VLSI CIRCUITS; WHITE NOISE;

BLOCK CODED MODULATION; BLOCK ORIENTED ALGORITHMS; CMOS TECHNOLOGY; DECODERS; DECODING RATE; GENERALIZED CONCATENATION; QUANTIZERS; SIGNAL SPACE CODES; VITERBI ALGORITHMS;

SYSTOLIC ARRAYS;

EID: 0029345683 PISSN: 09225773 EISSN: 1573109X Source Type: Journal
DOI: 10.1007/BF02407033 Document Type: Article

Times cited : (1)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.