A Performance-Driven Placement Tool for Analog Integrated Circuits

IEEE Journal of Solid-State Circuits

Volumn 30, Issue 7, 1995, Pages 773-780

  Lampaert, Koen ^a   Gielen, Georges ^a   Sansen, Willy M ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CALCULATIONS; CONSTRAINT THEORY; GEOMETRY; ITERATIVE METHODS; OPTIMIZATION; PERFORMANCE; RANDOM PROCESSES; SIMULATED ANNEALING;

ANALOG INTEGRATED CIRCUITS; CIRCUIT LOADING EFFECTS; DEVICE MISMATCHES; LAYOUT INDUCED PERFORMANCE DEGRADATION; SYMMETRY CONSTRAINTS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029345604     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.391116     Document Type: Article

References (11)

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