Architecture For A Low Complexity Rate-Adaptive Reed-Solomon Encoder

IEEE Transactions on Computers

Volumn 44, Issue 7, 1995, Pages 938-942

  Hasan, M A ^a   Bhargava, V K ^b  

^a UNIVERSITY OF WATERLOO   (Canada)

^b UNIVERSITY OF VICTORIA   (Canada)

Author keywords

Bit serial structure; finite field multiplication; generator polynomial; rate adaptive Reed Solomon encoder; triangular basis

Indexed keywords

CALCULATIONS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; ENCODING (SYMBOLS); ERROR CORRECTION; LOGIC GATES; POLYNOMIALS; VLSI CIRCUITS;

BIT SERIAL STRUCTURE; FINITE FIELD MULTIPLICATION; GENERATOR POLYNOMIAL; RATE ADAPTIVE REED SOLOMON ENCODER; TRIANGULAR BASIS;

CODES (SYMBOLS);

EID: 0029343883     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.392853     Document Type: Article

References (7)

1. MA. Hasan and V.K. Bhargava, “A VLSI architecture for a low complexity rate-adaptive Reed-Solomon encoder,” Proc. 16th Biennial Symp. Communications, Kingston, Ontario, pp. 331-334, May 1992.
2. R. Lidl and H. Niederreiter, Introduction to Finite Fields and Their Applications. Cambridge: Cambridge Univ. Press, 1986.
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4. M.Z. Wang and IF. Blake, “Bit serial multiplication in finite fields,” S1AMJ. Disc. Math., vol. 3, pp. 140-148, Feb. 1990.
5. M.A. Hasan and V.K. Bhargava, “Division and bit-serial multiplication over GF(0”. IEEE Proc. Part E, vol. 139, pp. 230-236, May 1992.
6. I.-S. Hsu, IS. Reed, T.K. Truong, K. Wang, C.S. Yeh, and L.J. Deutsch, “The VLSI implementation of a Reed-Solomon encoder using Berlekamp's bit-serial multiplier algorithm,” IEEE Trans. Computers, vol. 33, pp. 906-911, Oct. 1984.
7. N. Zierler and J. Brilluart, “On primitive trinomials (mod 2),” Inform. and Contr., vol. 13, pp. 541-554, 1968.