Calculation of the Soft Error Rate of Submicron CMOS Logic Circuits

IEEE Journal of Solid-State Circuits

Volumn 30, Issue 7, 1995, Pages 830-834

  Juhnke, T ^a   Klar, H ^a  

^a TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC SPACE CHARGE; ERROR ANALYSIS; INTEGRATED CIRCUIT MANUFACTURE; MULTIPLYING CIRCUITS; PIPELINE PROCESSING SYSTEMS; SEMICONDUCTOR JUNCTIONS; SHIFT REGISTERS;

CMOS LOGIC CIRCUITS; DYNAMIC PIPELINE REGISTERS; SOFT ERROR RATE; SUPPLY VOLTAGE;

LOGIC CIRCUITS;

EID: 0029342231     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.391126     Document Type: Article

References (8)

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