Advanced TFT SRAM cell technology using a phase-shift lithography

IEEE Transactions on Electron Devices

Volumn 42, Issue 7, 1995, Pages 1305-1313

  Yamanaka, Toshiaki ^a   Hashimoto, Takashi ^a   Hasegawa, Norio ^a   Tanaka, Toshihiko ^a   Hashimoto, Naotaka ^a   Shimizu, Akihiro ^a   Ohki, Nagatoshi ^a   Ishibashi, Koichiro ^a   Sasaki, Katsuro ^a   Nishida, Takashi ^a   Mine, Toshiyuki ^a   Takeda, Eiji ^a   Nagano, Takahiro ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; EQUIVALENT CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; ION IMPLANTATION; LEAKAGE CURRENTS; LITHOGRAPHY; MOS DEVICES; PHASE SHIFT; RANDOM ACCESS STORAGE; THIN FILM TRANSISTORS;

CELL RATIO; CHANNEL IMPLANTATION; MEMORY CELL TECHNOLOGY; MULTILAYER GATE INSULATOR; PHASE SHIFT LITHOGRAPHY; STATIC RANDOM ACCESS MEMORY (SRAM);

DATA STORAGE EQUIPMENT;

EID: 0029342113     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.391213     Document Type: Article

References (18)