Use of a Monte Carlo wiring yield simulator to optimize design of random logic circuits for yield enhancement

IEICE Transactions on Electronics

Volumn E78-C, Issue 7, 1995, Pages 852-857

  Fukuhara, Hideyuki ^a   Komatsuzaki, Takao ^a   Boku, Katsushi ^a   Miyai, Yoichi ^a  

^a Texas Instruments Japan Ltd   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; DEFECTS; ELECTRIC WIRING; GEOMETRY; MONTE CARLO METHODS; OPTICAL DEVICES; OPTIMIZATION;

DEFECT SIZE DISTRIBUTION FUNCTION; MONTE CARLO WIRING YIELD SIMULATOR; RANDOM LOGIC CIRCUITS; YIELD ENHANCEMENT;

LOGIC CIRCUITS;

EID: 0029336029     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (3)